{"title":"提高缓存分区池化NVMe ssd的I/O性能和公平性","authors":"Jiaojiao Wu;Li Cai;Zhigang Cai;Fengxiang Zhang;Jianwei Liao","doi":"10.1109/TCAD.2025.3553778","DOIUrl":null,"url":null,"abstract":"Nonvolatile memory express (NVMe) solid-state drives (SSDs) have become mainstream storage devices in today’s computing systems, due to their high throughput and ultralow latency. It has been observed that the impact of interference among all concurrently running streams (i.e., I/O workloads) on their overall responsiveness differs significantly in multistream SSDs, resulting in unfairness. This article proposes a cache division management scheme built on top of the evenly partition scheme for NVMe SSDs, to enhance I/O responsiveness without consciously sacrificing fairness. To this end, we first build a mathematical model to directly cut portions from the Local cache partitions allocated to concurrently running streams, considering their run-time performance measures. Then, our approach pools these portions together for the use of all streams. As a result, each stream has its corresponding Local cache space for ensuring fairness, meanwhile the pooled Global cache space is shared by all streams for enhancing I/O responsiveness. Trace-driven simulation experiments demonstrate that our proposal reduces the overall I/O latency by up to <monospace>24.4</monospace>%, and improve the measure of fairness by <inline-formula> <tex-math>$\\mathtt{2.5}\\times $ </tex-math></inline-formula> on average, in contrast to existing cache management schemes for NVMe SSDs.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3710-3723"},"PeriodicalIF":2.9000,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improving I/O Performance and Fairness in NVMe SSDs With Pooling Portions of Cache Partitions\",\"authors\":\"Jiaojiao Wu;Li Cai;Zhigang Cai;Fengxiang Zhang;Jianwei Liao\",\"doi\":\"10.1109/TCAD.2025.3553778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nonvolatile memory express (NVMe) solid-state drives (SSDs) have become mainstream storage devices in today’s computing systems, due to their high throughput and ultralow latency. It has been observed that the impact of interference among all concurrently running streams (i.e., I/O workloads) on their overall responsiveness differs significantly in multistream SSDs, resulting in unfairness. This article proposes a cache division management scheme built on top of the evenly partition scheme for NVMe SSDs, to enhance I/O responsiveness without consciously sacrificing fairness. To this end, we first build a mathematical model to directly cut portions from the Local cache partitions allocated to concurrently running streams, considering their run-time performance measures. Then, our approach pools these portions together for the use of all streams. As a result, each stream has its corresponding Local cache space for ensuring fairness, meanwhile the pooled Global cache space is shared by all streams for enhancing I/O responsiveness. Trace-driven simulation experiments demonstrate that our proposal reduces the overall I/O latency by up to <monospace>24.4</monospace>%, and improve the measure of fairness by <inline-formula> <tex-math>$\\\\mathtt{2.5}\\\\times $ </tex-math></inline-formula> on average, in contrast to existing cache management schemes for NVMe SSDs.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 10\",\"pages\":\"3710-3723\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2025-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10937118/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10937118/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Improving I/O Performance and Fairness in NVMe SSDs With Pooling Portions of Cache Partitions
Nonvolatile memory express (NVMe) solid-state drives (SSDs) have become mainstream storage devices in today’s computing systems, due to their high throughput and ultralow latency. It has been observed that the impact of interference among all concurrently running streams (i.e., I/O workloads) on their overall responsiveness differs significantly in multistream SSDs, resulting in unfairness. This article proposes a cache division management scheme built on top of the evenly partition scheme for NVMe SSDs, to enhance I/O responsiveness without consciously sacrificing fairness. To this end, we first build a mathematical model to directly cut portions from the Local cache partitions allocated to concurrently running streams, considering their run-time performance measures. Then, our approach pools these portions together for the use of all streams. As a result, each stream has its corresponding Local cache space for ensuring fairness, meanwhile the pooled Global cache space is shared by all streams for enhancing I/O responsiveness. Trace-driven simulation experiments demonstrate that our proposal reduces the overall I/O latency by up to 24.4%, and improve the measure of fairness by $\mathtt{2.5}\times $ on average, in contrast to existing cache management schemes for NVMe SSDs.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.