IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"TRAGIC: Test Oracle Generation for ISA Compliance Testing via Large Language Model","authors":"Zhihao Xu;Bixin Li;Xiaoning Du;Lulu Wang;Li Liao;Ying Zhou","doi":"10.1109/TCAD.2025.3632771","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3632771","url":null,"abstract":"Reduced instruction set computing – five (RISC-V) is one of the latest instruction set architectures (ISAs). It features an extremely modular and extensible design that makes it suitable for a variety of applications, from embedded systems to large computing systems. However, its inherent customizability and open nature also present challenges in terms of compliance and standardization. Traditionally, the validation relies on Spike as the reference simulator to generate compliance test oracles. Nevertheless, research has demonstrated that Spike may contain bugs, which may compromise the reliability of the generated test oracles. Therefore, developing new cross-validation methods has become increasingly important. To address this challenge, we propose test oracle generation for ISA compliance (TRAGIC), a method for generating compliance test oracles for RISC-V compliance testing based on large language models (LLMs). Different from traditional software testing, ISA compliance testing demands a finer-grained multidimensional test oracle, including not only the program outputs but also the detailed program states, such as key registers and memory addresses. Furthermore, long instruction sequences frequently exceed the context limitations of LLMs, and direct reasoning under such conditions leads to a notable degradation in accuracy. Therefore, TRAGIC employs a hierarchical strategy with two key components. First, the block segmentation component (BSC) decomposes complex test cases into manageable subtasks by analyzing the control flow and applying block slicing techniques. The segmentation both preserves the original program semantics and reduces the reasoning context, thereby enhancing inference accuracy. Second, the graph of inference component (GIC) performs structured reasoning on these subtasks using explicitly designed chain-of-thought (CoT) prompts. We utilize LLM to dynamically infer the output of each subtask and determine the next block to execute, continuing this iterative process until the entire task is completed. Meanwhile, key register and memory address tables are maintained and integrated into the final test oracle. By combining the BSC and the GIC, TRAGIC effectively mitigates the accuracy loss associated with long context information and enhances the accuracy of test oracle generation. TRAGIC passes the evaluation on the official RISC-V compliance test suite with manually written test cases. Furthermore, we also show that when integrated with automated test generation tools, our method found six bugs, 2 of which were previously unknown.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3264-3275"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction","authors":"Liwei Ni;Jiaxi Zhang;Shenggen Zheng;Junfeng Liu;Xingyu Meng;Biwei Xie;Xingquan Li;Huawei Li","doi":"10.1109/TCAD.2025.3628790","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3628790","url":null,"abstract":"Boolean equivalence allows Boolean networks with identical functionality to exhibit diverse graph structures. This gives more room for exploration in logic optimization while also posing a challenge for tasks involving consistency between Boolean networks. To tackle this challenge, we introduce BoolSkeleton, a novel Boolean network skeletonization method that improves the consistency and reliability of design-specific evaluations. BoolSkeleton comprises two key steps: preprocessing and reduction. In preprocessing, the Boolean network is transformed into a defined Boolean dependency graph, where nodes are assigned the functionality-related status. Next, the homogeneous and heterogeneous patterns are defined for the node-level pattern reduction step. Heterogeneous patterns are preserved to maintain critical functionality-related dependencies, while homogeneous patterns can be reduced. Parameter <inline-formula> <tex-math>$K$ </tex-math></inline-formula> of the pattern further constrains the fan-in size of these patterns, enabling fine-tuned control over the granularity of graph reduction. To validate BoolSkeleton’s effectiveness, we conducted four analysis/downstream tasks around the Boolean network: compression analysis, classification, critical path analysis, and timing prediction, demonstrating its robustness across diverse scenarios. Furthermore, it improves above 55% in the average accuracy compared to the original Boolean network for the timing prediction task. These experiments underscore the potential of BoolSkeleton to enhance design consistency in logic synthesis.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3238-3251"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Differentiated Privacy-Preserving Task Assignment Scheme Based on Generative Adversarial Networks in Spatial Crowdsourcing","authors":"Caixia Ma;Weishuo Yuan;Xinyi Wang;Chunfu Jia;Ruizhong Du;Guanxiong Ha","doi":"10.1109/TCAD.2025.3638261","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3638261","url":null,"abstract":"The spatial crowdsourcing (SC) can quickly assign tasks and obtain feedback based on task requirements and workers’ locations, which brings great convenience to task assignment. However, sensitive information can also be easily obtained by SC platforms. To prevent information leakage, various privacy-preserving task assignment schemes have been proposed. However, existing schemes have low query efficiency and may leak pattern privacy, task content, or worker preference. To address the above challenges, this article proposes a differentiated privacy-preserving task assignment scheme based on generative adversarial networks in spatial crowdsourcing (DPGAN-SC). This scheme leverages generative adversarial networks (GANs) to generate disguised locations for both tasks and workers, which are then used in the task-matching process. Within the standard area range, no location can be distinguished, ensuring location privacy while preventing adversaries from analyzing search patterns through matching results. The combination of location disguise and task content encryption makes it impossible for adversaries to infer worker preferences and access patterns through the matching process. In addition, to meet differentiated privacy requirements, DPGAN-SC leverages GANs to design a three-level privacy-classification mechanism. This mechanism categorizes private data while minimizing unnecessary privacy overhead. Compared with existing schemes, DPGAN-SC improves query efficiency by 100 times while ensuring the comprehensive privacy preservation.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3441-3454"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Overhead CNN Acceleration via FFT-Based Circular Convolution and Partially Pipelined Dataflow","authors":"Yishuo Meng;Jianfei Wang;Qiang Fu;Siwei Xiang;Jia Hou;Zhijie Lin;Ge Li;Chen Yang","doi":"10.1109/TCAD.2025.3636454","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3636454","url":null,"abstract":"Fast Fourier transform (FFT) has been widely recognized as an effective method for reducing the computational density of convolutional neural networks (CNNs). However, existing FFT-based CNN accelerators fail to fully exploit the algorithmic advantages of FFT while introducing significant additional hardware overhead. Consequently, this article tries to figure out how to fully implement the benefit of FFT while saving the transformation overhead. First, we propose a CirConv-based multiplication reduction (CMR) algorithm, which leverages circular convolution and Hermitian Symmetry to eliminate unnecessary padding and optimize FFT scale selection. Building upon this algorithm, we further design a partially pipelined transformation-computation (PPTC) dataflow to reduce the parallelism and hardware complexity of the FFT transformation. With the aid of the proposed CMR algorithm and PPTC dataflow, a high-throughput FFT-based CNN accelerator is implemented on a Xilinx VCU118 field programmable gate array (FPGA) platform, operating at 250 MHz. The experimental results demonstrate that, by combining Hermitian symmetry and PPTC dataflow, the look-up table (LUT) overhead for FFT/inverse fast Fourier transform (IFFT) operations can be reduced to only 12.14% of the original. Furthermore, while deploying VGG16, the inference performance of our designed accelerator is 6213 giga operations per second (GOPS), achieving a <inline-formula> <tex-math>$2.17times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$29.31times $ </tex-math></inline-formula> improvement in actual performance and a <inline-formula> <tex-math>$1.11times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$6.97times $ </tex-math></inline-formula> enhancement in DSP efficiency compared with the current works.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3276-3290"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"URoute: Universal Routability Prediction","authors":"Zhenkun Lin;Yibo Lin;Genggeng Liu;Gang Du","doi":"10.1109/TCAD.2025.3636449","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3636449","url":null,"abstract":"Deep learning has emerged as the predominant technique for predicting routability in very-large-scale-integrated (VLSI) circuits. However, it often struggles to generalize to various tasks and performs poorly when addressing inherent data imbalance issues in electronic design automation (EDA). Overcoming these challenges typically requires retraining or fine-tuning models, which poses significant difficulties for chip engineers who lack resources and expertise in neural network training. In light of this, we propose and address the universal problem of routability prediction for the first time. By framing this issue as a meta-learning scenario, we propose a few-shot learning (FSL)-based approach, URoute, which adapts flexibly to new tasks by utilizing features of the query chip and labeled examples without additional training. To tackle the data imbalance problem, we further propose a meta-learning strategy based on importance sampling to optimize the model training process. To validate the generality and adaptability of URoute, we construct an FSL dataset based on CircuitNet and ISPD2015 datasets. Experimental results demonstrate that URoute exhibits greater robustness and flexibility compared to existing methods when handling unseen routability prediction tasks, achieving competitive results.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3183-3196"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Unsupervised Learning-Based Multidimensional Scaling Approach for Placement and Routing of Monolithic Microwave Integrated Circuit","authors":"Yifan Wu;Junchao Wang;Jiayu Chen;Yaqi Wang;Bin You;Jun Liu","doi":"10.1109/TCAD.2025.3636445","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3636445","url":null,"abstract":"The layout method for radio frequency/monolithic microwave integrated circuit (RF/MMIC) is one of the key components in achieving MMIC design automation. This work proposes a multistage progressive automated layout framework addressing MMIC layout challenges under 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaAs pseudomorphic high electron mobility transistor (pHEMT) technology. This framework employs dimensionality reduction from unsupervised learning, integrates practical layout design rules, and achieves automated layout through analytical optimization methods. Applied to multiple cases including filters, low-noise amplifiers (LNAs), and power amplifiers (PAs), the method successfully generated manufacturable layouts; the process achieves end-to-end automation from placement to routing, producing layouts that are verified to be design rule check (DRC) clean. Simulation-verified results demonstrate comparable performance to manual designs while achieving <inline-formula> <tex-math>$ge 10times $ </tex-math></inline-formula> speedup over conventional methods. We believe this work contributes valuable attempts toward automated MMIC layout generation and advances progress in MMIC design automation.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3169-3182"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Security, Stability, and Overhead: Configuration Design Study and Experimental Validation of XOR-ed Physical Unclonable Functions","authors":"Gaoxiang Li;Yu Zhuang","doi":"10.1109/TCAD.2025.3631595","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3631595","url":null,"abstract":"The rapid growth of resource-constrained Internet of Things (IoT) and edge devices necessitates lightweight, robust security solutions. Delay-based physical unclonable functions (PUFs), particularly <sc>xor</small> arbiter PUFs (XOR APUFs), have emerged as promising alternatives due to their low hardware requirements and intrinsic security. However, traditional XOR APUFs face significant challenges in balancing reliability, security against modeling attacks, and hardware overhead. In this study, we explore new configurations of component-differential challenged XOR APUFs, a group of existing but underexplored PUFs that, we have found, hold promise for high performance in security, reliability, and overhead. Our study is focused on PUFs deployed on FPGAs, which are commonly used for reconfigurable computing/communication devices. Our FPGA-based experimental evaluations validate that our proposed PUFs achieve remarkable improvements in reliability and security, with minimal hardware overhead. Moreover, we outline the practical applicability of CDC-XOR PUFs in critical contemporary scenarios, including secure authentication for edge-AI devices, secure client enrollment in federated learning setups, and robust device management within industrial IoT (IIoT) environments. By effectively addressing the critical security-performance tradeoff, our proposed approach provides a compelling and scalable authentication solution well-suited for broad integration in modern IoT and edge computing ecosystems.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3143-3154"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale","authors":"Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori","doi":"10.1109/TCAD.2025.3632198","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3632198","url":null,"abstract":"Uncertainty estimation in neural networks (NNs) is vital in improving reliability and confidence in predictions, particularly in safety-critical applications. Bayesian neural networks (BayNNs) with dropout as an approximation offer a systematic approach to quantifying uncertainty, but they inherently suffer from high hardware overhead in terms of power, memory, and computation. Thus, the applicability of BayNNs to edge devices with limited resources or to high-performance applications is challenging. Some of the inherent costs of BayNNs can be reduced by accelerating them in hardware on a computation-in-memory (CIM) architecture with spintronic memories and binarizing their parameters. However, numerous stochastic units are required to implement conventional dropout-based BayNN. In this article, we propose the Scale-Dropout, a novel regularization technique for binary neural networks (BNNs), and Monte Carlo-Scale Dropout (MC-Scale Dropout)-based BayNNs for efficient uncertainty estimation. Our approach requires only one stochastic unit for the entire model, irrespective of the model size, leading to a highly scalable Bayesian NN. Furthermore, we introduce a novel spintronic memory-based CIM architecture for the proposed BayNN that achieves more than <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> energy savings compared with the state-of-the-art. We validated our method to show up to 1% improvement in predictive performance and superior uncertainty estimates compared with related works.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3113-3128"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization","authors":"Peng Xu;Su Zheng;Yuyang Ye;Chen Bai;Siyuan Xu;Hao Geng;Tsung-Yi Ho;Bei Yu","doi":"10.1109/TCAD.2025.3628787","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3628787","url":null,"abstract":"Electronic design automation (EDA) tools are critical in the very large scale integration (VLSI) flow. To address the challenges posed by the extensive search space and intricate feature interactions, statistical and machine learning methods have been employed. These methods aim to model tool parameters and treat the tuning process as a regression task. However, these regression-based methods suffer from inaccurate estimations owing to limited training samples. To address this issue, we propose a ranking-based tool parameter tuning framework, called RankTuner, which directly learns the dominant relationship between parameters. RankTuner utilizes a pairwise Gaussian process (GP) to estimate the probability and uncertainty of the dominance relationship. Our approach also integrates a Duel–Thompson sampling method to balance exploration and exploitation in parameter selections. A dimensionality reduction scheme with random embedding and trust region (TR) techniques is incorporated to enable parallel searches. Experimental results demonstrate the superiority of RankTuner compared to the cutting-edge tool parameter tuning methods.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3197-3210"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2026.3689828","DOIUrl":"https://doi.org/10.1109/TCAD.2026.3689828","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"C2-C2"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11527414","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}