IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"SPIRAL+: Efficient Signal–Power Integrity Co-Analysis for Interchiplet Links Validation","authors":"Xiao Dong;Songyu Sun;Yangfan Jiang;Jingtong Hu;Dawei Gao;Zhiguo Shi;Cheng Zhuo","doi":"10.1109/TCAD.2025.3532822","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3532822","url":null,"abstract":"Chiplet technology has recently emerged as a promising solution to improving chip performance through the modularization of complex designs and communication facilitated by high-speed interchiplet serial links. However, the increasing on-package routing density and data rates of these links introduce complex signal and power integrity challenges, surpassing those encountered in traditional large monolithic chips. Addressing these complexities with efficient analysis and design tools is crucial for maintaining design robustness. In this article, we propose SPIRAL+: signal-power integrity co-analysis framework for high-speed interchiplet serial links validation. The framework employs machine learning (ML) to construct transmitter models and utilizes an impulse response extraction method for modeling the channel and receiver. It then performs signal-power integrity co-analysis through a novel double-edge response-based method, leveraging the developed equivalent models. Additionally, an efficient ML model is crafted to accurately predict eye diagram metrics. The analysis provides valuable insights for design optimization. Experimental results show that SPIRAL+ achieves eye diagrams with a mean relative error of 0.07%–7.47%, while realizing a speedup of <inline-formula> <tex-math>$31times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$326times $ </tex-math></inline-formula> over traditional commercial tools.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"3140-3153"},"PeriodicalIF":2.7,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144657382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DasAtom: A Divide-and-Shuttle Atom Approach to Quantum Circuit Transformation","authors":"Yunqi Huang;Dingchao Gao;Shenggang Ying;Sanjiang Li","doi":"10.1109/TCAD.2025.3532818","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3532818","url":null,"abstract":"neutral atom (NA) quantum systems are emerging as a leading platform for quantum computation, offering superior or competitive qubit count and gate fidelity compared to superconducting circuits and ion traps. However, the unique features of NA devices, such as long-range interactions, long qubit coherence time, and the ability to physically move qubits, present distinct challenges for quantum circuit compilation. In this article, we introduce DasAtom, a novel divide-and-shuttle atom approach designed to optimize Quantum circuit transformation for NA devices by leveraging these capabilities. DasAtom partitions circuits into subcircuits, each associated with a qubit mapping that allows all gates within the subcircuit to be directly executed. The algorithm then shuttles atoms to transition seamlessly from one mapping to the next, enhancing both execution efficiency and overall fidelity. For a 30-qubit Quantum Fourier Transform (QFT), DasAtom achieves a <inline-formula> <tex-math>$415.8times $ </tex-math></inline-formula> improvement in fidelity over the move-based algorithm Enola and a <inline-formula> <tex-math>$10.6times $ </tex-math></inline-formula> improvement over the SWAP-based algorithm Tetris. Notably, this improvement is expected to increase exponentially with the number of qubits, positioning DasAtom as a highly promising solution for scaling quantum computation on NA platforms.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"2966-2978"},"PeriodicalIF":2.7,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144657473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approx-T: Design Methodology for Approximate Multiplication Units via Taylor-Expansion","authors":"Yao Shangshang","doi":"10.1109/TCAD.2025.3532845","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3532845","url":null,"abstract":"Approximate computing is emerging as a promising approach to devising energy-efficient IoT systems by exploiting the inherent error-tolerant nature of various applications. In this article, we present Approx-T, to tackle several major challenges according to the prior state-of-the-art (SOTA) approximate multiplication units (AMUs)—lack of comprehensive optimization formulation, asymmetric error distribution, nonadjustable runtime precision, and exponentially growing area complexity when adding up error compensation levels. We innovatively conduct an in-depth study on approximate multiplier via Taylor-expansion to address these issues. 1) Incorporate the Taylor’s theorem into the design concept of approximate arithmetic multipliers. 2) Leverage the inherent symmetrical error distribution of Taylor series to conduct unbiased approximations. 3) Present a runtime configurable error compensation architecture with low-complexity arithmetic operations. We implemented both approximate unsigned and signed integer and floating multiplication arithmetic units and compared with the SOTA works. The experimental results demonstrate that Approx-T surpasses other designs in all metrics, encompassing precision, area utilization, and power consumption. Furthermore, when deployed on an embedded field programmable gate array platform to assess a spectrum of edge computing tasks, Approx-T showcases remarkable performance. Particularly in CNN applications, it achieves up to a <inline-formula> <tex-math>$10.7times $ </tex-math></inline-formula> enhancement in energy efficiency, while maintaining negligible impact on accuracy.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"2856-2869"},"PeriodicalIF":2.7,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144657482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GNN-Based Timing Prediction in Prerouting Stage With Multitask Learning Strategy","authors":"Zihao Lin;Haisen Zhang;Peng Gao;Fei Yu;Tingting Wu;Xiaoming Xiong;Shuting Cai","doi":"10.1109/TCAD.2025.3532823","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3532823","url":null,"abstract":"Static timing analysis tools are commonly used to evaluate timing performance and guide optimization during placement stage. However, traditional timing analysis struggles to fast and accurately evaluate timing violation due to absence of detailed routing information necessary for RC parasitic parameter extraction. Therefore, a timing analyzer based on graph neural network is proposed in this article. Compared to previous works, a novel representation of circuit delay model is proposed in this article, employing timing arcs and virtual pins to predict net delay and arrival time (AT) in the prerouting phase. Additionally, to our knowledge, this is the first attempt to improve the quality of timing analyzer through a strategy of multitask learning, with the proposed enhanced dynamic weight average method. The experimental results demonstrate that our model excels in predicting net delay and AT, with average correlations of 0.9540 and 0.9058, respectively, on the testing set. In comparison to the previous state-of-the-art methods, our approach maintains accuracy in net delay prediction while enhancing the overall <inline-formula> <tex-math>$R^{2}$ </tex-math></inline-formula> score for AT prediction by 0.0271. Additionally, our method reduces inference time by 25.8%.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"3154-3164"},"PeriodicalIF":2.7,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144662896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information","authors":"","doi":"10.1109/TCAD.2024.3525201","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3525201","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 2","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10848361","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2024.3525199","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3525199","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 2","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10848247","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IncreMacro: Incremental Macro Placement Refinement","authors":"Yuan Pu;Tinghuan Chen;Zhuolun He;Jiajun Qin;Chen Bai;Haisheng Zheng;Yibo Lin;Bei Yu","doi":"10.1109/TCAD.2025.3531776","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3531776","url":null,"abstract":"This article proposes <inline-formula> <tex-math>$textsf {IncreMacro}$ </tex-math></inline-formula>, a novel approach for macro placement refinement in the context of integrated circuit (IC) design. The suggested approach iteratively and incrementally optimizes the placement of macros in order to enhance IC layout routability and timing performance. To achieve this, <inline-formula> <tex-math>$textsf {IncreMacro}$ </tex-math></inline-formula> utilizes several methods, including kd-tree-based macro diagnosis, gradient-based macro shifting, constraint-graph-based LP for macro legalization, and diffusion-based cell migration. By employing these techniques iteratively, <inline-formula> <tex-math>$textsf {IncreMacro}$ </tex-math></inline-formula> meets two critical solution requirements of macro placement: 1) pushing macros toward the chip boundary and 2) preserving the original macro relative positional relationship. The proposed approach has been incorporated into <inline-formula> <tex-math>$textsf {AutoDMP}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$textsf {DREAMPlace}~4.0$ </tex-math></inline-formula>, and is evaluated on seven RISC-V benchmark circuits and four TILOS macro placement circuit designs at the 7-nm technology node. Experimental results show that, compared with the macro placement solution provided by <inline-formula> <tex-math>$textsf {AutoDMP}~(textsf {DREAMPlace}~4.0$ </tex-math></inline-formula>), our approach reduces routed wirelength by 15.1% (14.9%), improves the routed worst negative slack (WNS) and total negative slack (TNS) by 99.9 (82.6%) and 99.9% (81.3%), and reduces the total power consumption by 4.4% (4.3%). Meanwhile, compared with <inline-formula> <tex-math>$textsf {IncreMacro}$ </tex-math></inline-formula> <xref>[1]</xref>, our approach augmented with the cell migration algorithm improves the routed WNS and TNS by 24.7% and 23.1%, and remains the average routed wirelength and total power consumption almost unchanged.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"3222-3235"},"PeriodicalIF":2.7,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10845818","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite Element Approach Based Numerical Framework for Device Simulator","authors":"Da-Wei Wang;Qing Zhang;Hang Wan;Wen-Sheng Zhao","doi":"10.1109/TCAD.2025.3531343","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3531343","url":null,"abstract":"In this work, a finite element method (FEM)-based numerical framework is proposed to effectively calculate the drift-diffusion equations and compiled into a parallel computing device simulator. In this framework, a novel upwind FEM is developed to solve the convection dominated continuity equations. In the implementation of the upwind method, the vector basis functions are employed to interpolate the edge streamline upwind (SU) current densities into mesh grid to obtain the spatial current density, and then the scalar FEM is used to construct the element matrix equation. Through comparing the calculating results of a 2-D PN-junction with those obtained by the COMSOL Semiconductor, the accuracy of proposed framework is verified first. Then, through several numerical cases, its advantages in comparison with FBSG-, SU Petrov Galerkin (SUPG)-, or control-volume-finite-element method SUPG-based frameworks in terms of mesh grid adaptivity, computing stability, and efficiency are presented. At last, by combining the proposed framework with a domain decomposition scheme and a fully coupled Newton’s approach, a parallel computing device simulator is developed, including both steady-state and transient solvers. The performance of the in-house simulator is evaluated in terms of calculating accuracy, large-scale problem solution capability, and scalabilities.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"3197-3207"},"PeriodicalIF":2.7,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System","authors":"Liyan Chen;Pengyu Liu;Dongxu Lyu;Jianfei Jiang;Qin Wang;Zhigang Mao;Naifeng Jing","doi":"10.1109/TCAD.2025.3531254","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3531254","url":null,"abstract":"Near data processing (NDP), enabled by near data accelerators (NDAs) within DIMM-based main memory, enhances performance by providing more aggregated bandwidth and reducing long-distance data transfers. While the performance of NDAs has received widespread attention, the overhead of host-NDA communication has been overlooked, becoming a bottleneck in NDP systems. To alleviate performance degradation from communication, we propose Bridge-NDP, the first NDP architecture that implements a workflow with efficient communication-computation overlap. Bridge-NDP is built upon the conventional NDP architecture and can be easily applied to existing NDP designs, regardless of the memory level where NDAs are attached. Specifically, we introduce a novel direct host-NDA communication method that utilizes existing memory buses as bridge buses, avoiding the need for new interconnections. It enables seamless integration with other memory accesses while achieving high bandwidth utilization with minimal hardware overhead. For the system-level workflow design, we optimize and extend existing dataflow to achieve richer computing paradigms with fewer redundant memory accesses. Additionally, we provide programming support with efficient API designs and data management to hide low-level resource details and ensure correctness guarantees. Comprehensive experiments demonstrate that Bridge-NDP achieves significant performance improvements, with speedups of <inline-formula> <tex-math>$1.8times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$3.1times $ </tex-math></inline-formula> and bandwidth utilization improvement of <inline-formula> <tex-math>$2.0times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$2.9times $ </tex-math></inline-formula> over the state-of-the-art NDP solutions.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"2939-2951"},"PeriodicalIF":2.7,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144657447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing","authors":"Zhenyu Wang;Pragnya Sudershan Nalla;Jingbo Sun;A. Alper Goksoy;Sumit K. Mandal;Jae-Sun Seo;Vidya A. Chhabria;Jeff Zhang;Chaitali Chakrabarti;Umit Y. Ogras;Yu Cao","doi":"10.1109/TCAD.2025.3531348","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3531348","url":null,"abstract":"Monolithic designs face significant fabrication cost and data movement challenges, especially when executing complex and diverse AI models. Advanced 2.5D/3D packaging promises high bandwidth and connection density to overcome these challenges, yet it also introduces new electro-thermal constraints. This article develops a suite of analytical performance models to enable efficient benchmarking of a 2.5D/3D heterogeneous system for energy-efficient AI computing. These models encompass various performance metrics related to computing units, network-on-chip (NoC), and network-on-package (NoP). The results are summarized into a new tool, HISIM, which is <inline-formula> <tex-math>$10^{4} times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$10^{6} times $ </tex-math></inline-formula> faster than state-of-the-art AI benchmark tools. Furthermore, HISIM integrates rapid thermal simulation for the 2.5D/3D system, helping shed light on both the potential and limitations of 2.5D/3D heterogeneous integration (HI) on representative AI algorithms. The code of HISIM is available at <uri>https://github.com/mec-UMN/HISIM</uri>.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 8","pages":"3208-3221"},"PeriodicalIF":2.7,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}