IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"NoiseGuard: A Comprehensive Framework With Noise Modeling, Noise-Aware Training, and Noise Compensation for In-Memory Computing SoC","authors":"Guangyao Wang;Yizhe Chen;Yuexi Lv;Hanjie Liu;Yuannuo Feng;Jenny Ma;Saiya Wang;Guilin Zhao;Meng Wang;Yixiang Zhang;Yong Pei;Minghua Tang;Wang Kang","doi":"10.1109/TCAD.2025.3626453","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3626453","url":null,"abstract":"Despite the tremendous potential of in-memory computing (IMC) for AI applications, analog IMC still faces critical challenges related to noise sensitivity and computational accuracy, largely due to intrinsic nonidealities. These limitations significantly restrict the scalability and real-world deployability of analog IMC systems. To address accuracy degradation caused by hardware noise, we propose a comprehensive framework integrating noise modeling, noise-aware training (NAT), and hardware-adaptive compensation (HAC). Specifically, a noise model is derived from empirical measurements of a 40-nm eFlash-based IMC system-on-chip (SoC) to capture diverse noise sources. The NAT scheme embeds the noise model into the training pipeline to enhance algorithm robustness, while the noise model guides HAC to mitigate the effects of device- and circuit-level variations during inference. The experimental results demonstrate that the noise model achieves a cosine similarity above 0.99 with actual chip behavior. In a speech denoising task, NAT improves the perceptual evaluation of speech quality (PESQ) by 0.168 (6.82%), while HAC reduces the output error variance by an average of 74.68%. Applied to multiple tasks including speech wake-up, speech denoising, and image super-resolution, our framework achieves improvements of 13.5% in wake-up accuracy, 0.7 (29.2%) in PESQ, and 2.82 dB (7.2%) in peak signal-to-noise ratio (PSNR), respectively. These results demonstrate the generality and effectiveness of the proposed framework across a range of AI tasks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2597-2610"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DomSim: Hardware-Aware Hybrid Fault Simulation With Dominator Tree-Guided Partitioning","authors":"Mingjun Wang;Hui Wang;Feng Gu;Zizhen Liu;Jianan Mu;Shengwen Liang;Zhongkai Yu;Zheng Liang;Jun Gao;Jiaping Tang;Jing Ye;Xiaowei Li;Bei Yu;Huawei Li","doi":"10.1109/TCAD.2025.3624173","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624173","url":null,"abstract":"Gate-level fault simulation is a critical step in design for test and functional safety verification of the chip design process, essential to ensuring circuit reliability. As chip complexity grows for mission-critical applications such as autonomous vehicles, medical devices, and military systems, the efficiency of fault simulation increasingly becomes a bottleneck in the chip’s time-to-market. However, existing methods often suffer from computational redundancy, inefficiencies in memory access, or failure to optimize performance for specific CPU hardware platforms. This article proposes DomSim, a hardware-aware hybrid fault simulation method that combines compiled simulation and event-driven simulation with an optimized computation-to-memory-access ratio. Using circuit information and hierarchical structure provided by dominator trees, DomSim achieves high-quality circuit partitioning, optimizing hardware resource utilization, and memory access locality. Furthermore, a parameter adjustment strategy tailored to hardware capabilities and circuit characteristics enables adaptive optimization. Extensive experiments show that DomSim surpasses a commercial tool by <inline-formula> <tex-math>$10.29times $ </tex-math></inline-formula> on average. Further experiments demonstrate that DomSim exhibits good adaptability across different hardware platforms and circuits, highlighting the superiority of our method.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2725-2738"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware Security Meets Incomplete Netlists: Insights Into Trojan Detection via Structural Reasoning","authors":"Decheng Qiu;Chen Dong;Bolun Li;Mingzhi Chen;Yang Yang","doi":"10.1109/TCAD.2025.3624082","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624082","url":null,"abstract":"In order to better utilize the achievements of various countries and lower costs, the integrated circuit (IC) design and manufacturing process is based on a global supply chain model, highly relying on untrusted third parties, such as intellectual property (IP) cores, electronic design automation (EDA) tools, and employees. This globalized model creates a lot of opportunities for the prosperity of hardware Trojans (HTs). However, existing countermeasures were all accomplished under some assumptions, such as finding HTs in a complete netlist. In practical industry scenarios, netlists may be obtained through reverse engineering, which has inherent limitations, including imaging resolution and inaccurate recognition of interconnections, making it almost impossible to obtain a complete netlist to detect whether HTs exist. Evidently, studying how to find HTs from incomplete netlists should be a reasonable, notable, critical, and practical issue for the IC security research community. Addressing this problem entails substantial challenges. This article is the first to propose the problem of detecting HTs with incomplete netlists and also presents an effective approach named HTINS, which infers and completes incomplete circuit structures and utilizes the completed information for HTs detection. The method leverages a graph variational autoencoder (GraphVAE) to reconstruct incomplete netlist components and performs circuit feasibility validation on the reconstructed components. Local features are then extracted from the completed circuits and classified via a graph neural network (GNN). In the experiments, netlist components are randomly removed to set netlists with 1%, 5%, and 10% missing ratios, and the performance of HT detection on the completed netlists is evaluated under these conditions. Experimental results demonstrate that the proposed method can effectively reconstruct incomplete netlists and significantly improve the HT detection performance.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2753-2766"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LEAP: Lightweight Neural Network Inference Through Proactive Early-Exiting Prediction","authors":"Yingtao Shen;Xiangjie Li;Yehan Ma;Weidong Cao;Jie Zhao;An Zou","doi":"10.1109/TCAD.2025.3621532","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3621532","url":null,"abstract":"In recent years, the incorporation of early-exit layers into deep neural networks has allowed inference to terminate earlier while maintaining accuracy. However, the passive decision-making involved in these static exit placements creates a dilemma: fine-grained placement may cause high performance and energy overhead due to frequent exit layer execution, while coarse-grained placement may miss early-exit opportunities. Moreover, common energy-saving techniques like adjusting processor configurations are not applicable once inference begins. To overcome these challenges and improve computation and energy efficiency, we propose lightweight neural network inference through proactive early-exiting prediction (LEAP), a software–hardware co-design approach. On the software side, LEAP proactively predicts exit points at runtime, reducing computation by enabling early exits without requiring every preplaced exit layer to be executed. On the hardware side, LEAP adjusts processor settings—such as frequency and voltage—based on single or multiple predicted exits to optimize energy consumption while adhering to latency requirements. Extensive experimental results show that LEAP significantly improves efficiency. Compared to standard inference, LEAP reduces computation by up to 76.4% and saves up to 83.2% in energy. Compared to state-of-the-art early-exit methods, LEAP achieves up to 27.9% less computation and 57.1% more energy savings, while maintaining similar accuracy and latency.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2799-2812"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AsyncGrid: An Intralayer and Interlayer Asynchronous Hybrid Parallelism System for Responsive Edge LLM Inference","authors":"Yi Xiong;Rui Zhang;Yulong Zu;Weihong Liu;Zongwei Zhu;Jiawei Geng;Boyu Li;Qianyue Cao;Xuehai Zhou","doi":"10.1109/TCAD.2025.3624135","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624135","url":null,"abstract":"Edge deployment of large language models (LLMs) is increasingly attractive due to its advantages in privacy, customization, and availability. However, edge environments face significant challenges in reducing time-to-first-token (TTFT). TTFT consists of: 1) queuing delay and 2) prefill latency, both of which are exacerbated by edge-resource constraints. The substantial computational demands of LLM inference grow superlinearly with prompt length, causing high prefill latency; and limited edge resources restrict prefill throughput, preventing the timely handling of incoming requests, thereby exacerbating queuing delays. Model parallelism is a commonly used solution in cloud-based systems, but directly applying it to edge environments proves ineffective. Intralayer parallelism [e.g., tensor/sequence parallelism (SP)] can reduce prefill latency but suffers from frequent global synchronization, which bottlenecks prefill throughput due to edge-limited interconnection bandwidth. Interlayer parallelism [e.g., pipeline parallelism (PP)] improves prefill throughput via fully asynchronous execution but retains high prefill latency due to stage-wise serialized computation. To address this dilemma, this article leverages the properties of the causal attention mechanism in LLMs and proposes intralayer asynchronous parallelism (IAP), which performs intralayer parallel computations to reduce prefill latency while avoiding global synchronization to mitigate prefill throughput bottlenecks. Moreover, considering communication sensitivity in intralayer parallelism, this article integrates IAP with interlayer asynchronous parallelism into a unified plan space. This hybrid parallelism adapts to diverse hardware and request loads, enabling more effective TTFT optimization. To enable the end-to-end implementation of this hybrid parallelism, this article proposes AsyncGrid, an LLM inference system tailored for responsive edge LLM inference. AsyncGrid: 1) models runtime overheads through a performance profiler; 2) employs an integer programming (IP) formulation to optimize execution plan, with the objective of minimizing latency while meeting throughput requirements; and 3) implements fine-grained communication optimization (FCO) during runtime. A comprehensive evaluation on an edge testbed demonstrates AsyncGrid’s significant advantages over existing methods, achieving substantial improvements in both homogeneous and heterogeneous settings.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2826-2839"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"eLDPC: An Elastic and Scalable LDPC-Decoder With Early Termination by Effectively Leveraging High-Level Synthesis","authors":"Shaohua Wang;Zhihao Zeng;Qiang Cao;Jiawei Yang;Yifan Zhang;Yekang Zhan;Jie Yao","doi":"10.1109/TCAD.2025.3625470","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3625470","url":null,"abstract":"Emerging communication and storage embrace low-density parity-check (LDPC) codes to fully exploit their physical channels. A field-programmable gate array (FPGA) is widely employed to fast prototype and accelerate the LDPC decoding with high complexity. For varying channel conditions, the FPGA decoder is desired to elastically stop iteration when meeting the success condition, avoiding conservatively performing a predefined and large number of iterations. However, the dynamical-execution algorithms with adjustable parameters generally are challenging for a scalable decoder structure, preferred to deterministic execution logic. To overcome the problem, this article presents an elastic and scalable HLS-based FPGA LDPC decoder architecture with early termination to achieve high throughput and flexibility. To this end, eLDPC first provides a universal operation, fully leveraging the features of HLS to efficiently implement optimized small-scale hardware units for low-level data-update operations. Second, eLDPC presents a decoding-iteration pipeline that adds a termination-check (TC) stage to terminate the following iteration for current codeword decoding. eLDPC also presents an HLS-enhanced approach to address memory access conflicts associated with the DU pipeline. Furthermore, eLDPC extends the number of DU decoding-iteration pipelines within a single stream to decode multiple codewords in parallel. Third, eLDPC designs elastic and independent multiple decoding streams by using FIFO queues to decouple the input, output, and a decoding unit (DU) with variable iterations while avoiding the potential blockage of the queueing. We implement and evaluate eLDPC on a Xilinx U55C. Experiments show that eLDPC outperforms recent decoders by up to <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> with the same parameter and achieves the actual decoding throughput of up to 49.5 Gb/s with high scalability and flexibility.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2693-2706"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware-Accelerated Algorithm for Complex Function Roots Density Graph Plotting","authors":"Ruibai Tang;Chengbin Quan","doi":"10.1109/TCAD.2025.3639508","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3639508","url":null,"abstract":"Solving and visualizing the potential roots of complex functions is essential in both theoretical and applied domains, yet often computationally intensive. We present a hardware-accelerated algorithm for complex function roots density graph plotting by approximating functions with polynomials and solving their roots using single-shift QR iteration. By leveraging the Hessenberg structure of companion matrices and optimizing QR decomposition with Givens rotations, we design a pipelined field-programmable gate array (FPGA) architecture capable of processing a large number of polynomials with high throughput. Our implementation achieves up to <inline-formula> <tex-math>$65times $ </tex-math></inline-formula> higher energy efficiency than CPU-based approaches, and while it trails modern GPUs in performance. Compared with state-of-the-art QR decomposition solutions, our design specifically optimizes QR decomposition for complex-valued Hessenberg matrices up to size <inline-formula> <tex-math>$6times6$ </tex-math></inline-formula>, exhibiting a moderate throughput of 16.5M QR decompositions per second, while prior works have predominantly focused on <inline-formula> <tex-math>$4times4$ </tex-math></inline-formula> general matrices.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2767-2771"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SparseMap: A Sparse Tensor Accelerator Framework Based on Evolution Strategy","authors":"Boran Zhao;Haiming Zhai;Zihang Yuan;Hetian Liu;Tian Xia;Wenzhe Zhao;Pengju Ren","doi":"10.1109/TCAD.2025.3621407","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3621407","url":null,"abstract":"The growing demand for sparse tensor algebra (SpTA) in machine learning and big data has driven the development of various sparse tensor accelerators (SpTAs). However, most existing manually designed accelerators are limited to specific scenarios, and it is time-consuming and challenging to adjust a large number of design factors when scenarios change. Therefore, automating the design of SpTA accelerators is crucial. Nevertheless, previous works focus solely on either mapping (i.e., tiling communication and computation in space and time) or sparse strategy (i.e., bypassing zero elements for efficiency), leading to suboptimal designs due to the lack of consideration of both. A unified framework that jointly optimizes both is urgently needed. However, integrating mapping and sparse strategies leads to a combinatorial explosion in the design space(e.g., as large as <inline-formula> <tex-math>$O(10^{41})$ </tex-math></inline-formula> for the workload <inline-formula> <tex-math>$P_{32 times 64} times Q_{64 times 48} = Z_{32 times 48}$ </tex-math></inline-formula>). This vast search space renders most conventional optimization methods [e.g., particle swarm optimization (PSO), reinforcement learning (RL), and Monte Carlo tree search (MCTS)] inefficient. To address this challenge, we propose an evolution strategy (ES)-based SpTA optimization framework, called SparseMap. SparseMap constructing a more essential-factor design space with the consideration of both mapping and sparse strategy. We introduce a series of enhancements to genetic encoding and evolutionary operators, enabling SparseMap to efficiently explore the vast and diverse design space. We quantitatively compare SparseMap with prior works and classical optimization methods, demonstrating that SparseMap consistently finds superior solutions.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2772-2786"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BuffeRS: A Buffer Reservation Scheduling Strategy for Router Bypassing in NoCs and Multichiplet Networks","authors":"Zixuan Liu;Xiaoma Wu;Yaoyao Ye","doi":"10.1109/TCAD.2025.3624677","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624677","url":null,"abstract":"Network-on-chip (NoC) is a crucial communication infrastructure for multiprocessor systems-on-chip (SoCs). The bypass flow control mechanism is an advanced NoC technique to reduce packet delay by enabling bufferless packet forwarding through direct path establishment. However, existing works either used inefficient contention-free path allocation methods or complex transmission protocols to ensure destination buffer availability, which significantly limited the efficiency of router bypassing. In this work, we propose a buffer reservation scheduling strategy (BuffeRS) for enhancing the performance of router bypassing by efficiently providing contention-free path allocation and destination buffer availability for bypass packets. It facilitates a dual-mode packet delivery scheme via conventional buffered routing paths and dynamically configured bypass paths, while ensuring buffer availability through coordinated time-division activation of router groups. For chiplet-based systems, we utilize BuffeRS on chiplet routers to enhance the intrachiplet bypass transmission efficiency, meanwhile utilizing BuffeRS on boundary routers to bypass interchiplet packets and subsequently resolve interchiplet deadlocks. Experimental evaluations have demonstrated that BuffeRS achieves substantial performance gains with a small hardware overhead for both monolithic SoCs and chiplet-based systems.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2635-2648"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Steady-State Thermal Analysis With Separation of Variables and Discrete Cosine Transform","authors":"Hao Ai;Liang Chen;Jianhua Zhang;Bei Yu;Wenxing Zhu","doi":"10.1109/TCAD.2025.3621892","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3621892","url":null,"abstract":"As performance continues to improve, excessive high temperatures will decrease reliability and complicate timing management of chips. In early stages of chip design, fast and accurate computation of 2-D temperature distribution is essential for effectively assessing thermal effects. Therefore, a highly efficient yet accurate 2-D thermal computation method is urgently needed. To this aim, this article proposes two efficient and precise 2-D steady-state temperature computation schemes based on the method of separation of variables. By proposing an accurate power density function, the analytical solution of the method can be computed explicitly. We show the convergence and error bound of the method, with the convergence error rate <inline-formula> <tex-math>$O(1/N^{2})$ </tex-math></inline-formula>, where <inline-formula> <tex-math>$N$ </tex-math></inline-formula> is the truncation order. This method is applied with discrete cosine transform (DCT) to compute the architecture-level steady-state temperature distribution with the same convergence error rate and the time complexity <inline-formula> <tex-math>$O(nMN+s^{2}log (s^{2}))$ </tex-math></inline-formula>, where <inline-formula> <tex-math>$s^{2}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$n$ </tex-math></inline-formula> are the total number of grids and the number of modules, respectively, and <inline-formula> <tex-math>$M$ </tex-math></inline-formula> and <inline-formula> <tex-math>$N$ </tex-math></inline-formula> are the truncation orders. The method for architecture level is further optimized with DCT for standard-cell-level full-chip thermal analysis, and an efficient computational method is proposed with time complexity <inline-formula> <tex-math>$O(s^{2}log (s^{2}))$ </tex-math></inline-formula>. The experimental results demonstrate that our single-threaded algorithms achieve a speedup of up to two–three orders of magnitude compared to SISOV (single-threaded) and COMSOL 6.0 (configured with 24 threads and Intel MKL), meanwhile maintain high simulation accuracy.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2649-2663"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}