IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献_第5页

Automated Generation of Benchmarks for Falsification of STL Specifications STL规范伪造基准的自动生成

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-11 DOI: 10.1109/TCAD.2025.3550410

Yipei Yan;Deyun Lyu;Zhenya Zhang;Paolo Arcaini;Jianjun Zhao

{"title":"Automated Generation of Benchmarks for Falsification of STL Specifications","authors":"Yipei Yan;Deyun Lyu;Zhenya Zhang;Paolo Arcaini;Jianjun Zhao","doi":"10.1109/TCAD.2025.3550410","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3550410","url":null,"abstract":"Falsification, whose aim is to detect unsafe behaviors of cyber-physical systems (CPS) that violate signal temporal logic (STL) specifications, has been actively investigated in the past decade. Although numerous falsification approaches have been proposed, the falsification community suffers from a shortage of benchmarks that hinders a thorough assessment of those falsification approaches. In this article, we bridge this gap by proposing an automated approach for generating falsification benchmarks. Our approach is data-driven: first, we generate different time-variant traces (acting as system output traces) that satisfy a given STL specification, and we associate these with corresponding system input traces; then, we use these input and output traces to train an LSTM model that generalizes them. These models can serve as benchmarks for assessing falsification approaches against the given specification. In the experimental evaluation, we validate the generated models by measuring their ability to differentiate the performance of different falsification approaches. Our generated models expose strengths and weaknesses of all the considered falsification approaches, which was not achieved by benchmarks currently used in the falsification community. These results demonstrate the usefulness of our approach and can potentially push forward subsequent research in falsification.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"4004-4017"},"PeriodicalIF":2.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits 大规模模拟电路的图学习增强子电路匹配

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-11 DOI: 10.1109/TCAD.2025.3549701

Jindong Tu;Yapeng Li;Pengjia Li;Peng Xu;Qianru Zhang;Sanping Wan;Yongsheng Sun;Bei Yu;Tinghuan Chen

{"title":"SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits","authors":"Jindong Tu;Yapeng Li;Pengjia Li;Peng Xu;Qianru Zhang;Sanping Wan;Yongsheng Sun;Bei Yu;Tinghuan Chen","doi":"10.1109/TCAD.2025.3549701","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3549701","url":null,"abstract":"Subcircuit matching in a large-scale analog circuit is a fundamental problem in VLSI computer-aided design (CAD). Existing approaches suffer from a poor scalability issue for a large-scale analog circuit. In this article, we propose a graph learning-boosted subcircuit matching framework for large-scale analog circuits named SMART, consisting of two stages. In the first stage, we customize hypergraph neural networks to map circuit topology for embedding space. Then, coarse subcircuit recognition is directly performed in the embedding space by geometric relations between the query circuit and all candidate subcircuits within the target circuit. In the second stage, a radial matching method, including device attribute matching, connection relationship matching and uniqueness-based matching, is customized to perform fine matching and obtain matches between interconnections and devices in the query circuit and candidate subcircuits. Experimental results show our SMART can outperform state-of-the-art search-based method VF3 and learning-based method NeuroMatch, and achieve the fastest speed. Specifically, using our framework for subcircuit matching can achieve up to <inline-formula> <tex-math>$135times $ </tex-math></inline-formula> speedup with slight accuracy loss, and up to <inline-formula> <tex-math>$7times $ </tex-math></inline-formula> speedup while maintaining 100% accuracy.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"4018-4031"},"PeriodicalIF":2.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Model Switching in RRAM-Based DNN Accelerators 基于随机存储器的DNN加速器的高效模型切换

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-11 DOI: 10.1109/TCAD.2025.3550403

Fang-Yi Gu;Ing-Chao Lin;Bing Li;Ulf Schlichtmann;Grace Li Zhang

{"title":"Efficient Model Switching in RRAM-Based DNN Accelerators","authors":"Fang-Yi Gu;Ing-Chao Lin;Bing Li;Ulf Schlichtmann;Grace Li Zhang","doi":"10.1109/TCAD.2025.3550403","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3550403","url":null,"abstract":"Resistive random access memory (RRAM) has emerged as a promising technology for deep neural network (DNN) accelerators, but programming every weight in a DNN onto RRAM cells for inference can be both time-consuming and energy-intensive, especially when switching between different DNN models. This article introduces a hardware-aware multimodel merging (HA3M) framework designed to minimize the need for reprogramming by maximizing weight reuse, while taking into account the hardware constraints of the accelerator. The framework includes three key approaches: 1) crossbar (XB)-aware model mapping (XAMM); 2) block-based layer matching (BLM); and 3) multimodel retraining (MMR). XAMM reduces the XB usage of the preprogrammed model on RRAM XBs while preserving the model’s structure. BLM reuses preprogrammed weights in a block-based manner, ensuring the inference process remains unchanged. MMR then equalizes the block-based matched weights across multiple models. Experimental results show that the proposed framework significantly reduces programming cycles in multi-DNN switching scenarios while maintaining or even enhancing accuracy, and eliminating the need for reprogramming.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3738-3751"},"PeriodicalIF":2.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation PARoute2：通过性能驱动制导生成增强的模拟路由

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-11 DOI: 10.1109/TCAD.2025.3550445

Peng Xu;Jindong Tu;Guojin Chen;Keren Zhu;Tinghuan Chen;Tsung-Yi Ho;Bei Yu

引用次数: 0

An Abstract Simulator for Species Concentrations in Channel-Based Microfluidic Devices 基于通道的微流控装置中物质浓度模拟

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-10 DOI: 10.1109/TCAD.2025.3549703

Michel Takken;Maria Emmerich;Robert Wille

{"title":"An Abstract Simulator for Species Concentrations in Channel-Based Microfluidic Devices","authors":"Michel Takken;Maria Emmerich;Robert Wille","doi":"10.1109/TCAD.2025.3549703","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3549703","url":null,"abstract":"The design of microfluidic devices, i.e., Lab-on-Chips (LoCs) or Micro Total Analysis Systems (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>TASs), is a tedious and cumbersome process with many time-consuming and costly fabrication cycles. Many of these devices contain dissolved species (i.e., solutes) that are required to appear in the system at specific predefined concentrations. The use of simulations can aid the design process of microfluidic devices. However, methods from Computational Fluid Dynamics (CFDs), which are commonly used, are computationally costly and require a lot of time to finish. In this work, we present a simulator for species concentrations in channel-based microfluidic devices that operates on a higher level of abstraction and is multiple orders of magnitude faster than CFD simulation methods. The simulator has been implemented in C++ and is benchmarked against CFD simulations as well as against measured results from experiments on a fabricated device. The results are analyzed and the applicability of the simulator for the simulation of microfluidic devices is assessed.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3764-3775"},"PeriodicalIF":2.9,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918827","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree ict：具有倾斜延迟负载树的迭代和分层时钟树合成

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-07 DOI: 10.1109/TCAD.2025.3549355

Weiguo Li;Zhipeng Huang;Bei Yu;Wenxing Zhu;Jian Chen;Zhixue He;Xingquan Li

{"title":"iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree","authors":"Weiguo Li;Zhipeng Huang;Bei Yu;Wenxing Zhu;Jian Chen;Zhixue He;Xingquan Li","doi":"10.1109/TCAD.2025.3549355","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3549355","url":null,"abstract":"The advancement of modern clock tree synthesis (CTS) encounters a bottleneck, primarily due to the difficulty in achieving multiobjective co-optimization among complex design processes. To concurrently optimize skew, latency, and load capacitance, we propose an iterative and hierarchical CTS framework, which is composed of clustering, topology generation and routing, buffering, and optimization. First, we introduce a capacitance-based metric to achieve adaptive balanced clustering and optimize the cluster results through simulated annealing. Second, to construct a clock tree with lower latency, load capacitance, and skew, we introduce the skew-latency-load tree (SLLT), which combines the advantages of bound skew tree and Steiner shallow-light tree, and we propose an effective SLLT construction algorithm. Third, to further optimize CTS result by buffering, we introduce the critical wirelength evaluation (CWE) to evaluate the capability of each buffer, and propose the insertion delay estimation (IDE) to reduce the evaluation bias during buffering, then design the iterative skew convergence algorithm (ISCA) to achieve complete convergence of skew. We validate our solution using 28 nm process technology. Compared to our method, the commercial tool increases skew, latency, and clock capacitance by 39.5%, 13.0%, and 18.5%, respectively, while the OpenROAD by 101.6%, 50.7%, and 25.5%, respectively.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3948-3961"},"PeriodicalIF":2.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multistage Enhanced Diagnosis With Fault Candidate Reduction 基于候选故障缩减的多阶段增强诊断

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-07 DOI: 10.1109/TCAD.2025.3549352

Hyojoon Yun;Hyeonchan Lim;Hayoung Lee;Sungho Kang

引用次数: 0

OATT: Outlier-Oriented Alternative Testing and Post-Manufacture Tuning of Analog/Mixed-Signal Circuits 面向异常值的替代测试和模拟/混合信号电路的制造后调谐

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-07 DOI: 10.1109/TCAD.2025.3549353

Suhasini Komarraju;Akhil Tammana;Chandramouli N. Amarnath;Abhijit Chatterjee

{"title":"OATT: Outlier-Oriented Alternative Testing and Post-Manufacture Tuning of Analog/Mixed-Signal Circuits","authors":"Suhasini Komarraju;Akhil Tammana;Chandramouli N. Amarnath;Abhijit Chatterjee","doi":"10.1109/TCAD.2025.3549353","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3549353","url":null,"abstract":"Modern analog mixed-signal (AMS) devices manufactured in advanced CMOS processes pose significant testing and post-manufacture tuning challenges. Measurement of the specifications of AMS components is generally difficult as this requires the use of a range of dedicated tests while defect-based testing on the other hand, requires extensive defect simulations that are compute-intensive. To overcome these limitations, this research proposes OATT; a testing and post-manufacture tuning approach for AMS circuits that is designed to stress the performance of the device under test (DUT), formalize a statistical (multidimensional Gaussian) distribution of the expected response of known “good” devices (inliers), and use test limits grounded in theoretical statistics to classify all out-of-distribution devices (outliers) as “bad.” It is an alternative test approach in that it does not explicitly target simulation of defect mechanisms. Tuning is performed to transform individual outlier DUT responses to those resembling inlier devices by modulating hardware tuning knobs, such as bias voltages and currents, using a reinforcement learning algorithm. Circuit simulations and hardware results demonstrate the viability and efficiency of the proposed approach.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3668-3682"},"PeriodicalIF":2.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient and Scalable Post-Layout Optimization for Field-Coupled Nanotechnologies 场耦合纳米技术的高效可扩展后布局优化

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-07 DOI: 10.1109/TCAD.2025.3549354

Simon Hofmann;Marcel Walter;Robert Wille

{"title":"Efficient and Scalable Post-Layout Optimization for Field-Coupled Nanotechnologies","authors":"Simon Hofmann;Marcel Walter;Robert Wille","doi":"10.1109/TCAD.2025.3549354","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3549354","url":null,"abstract":"As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field-coupled Nanocomputing (FCN), which operates through the repulsion of physical fields at the nanoscale, emerges as a promising alternative. However, realizing specific functionalities within this technology necessitates the development of dedicated FCN physical design methods. Although various methods have been proposed, their reliance on heuristic approaches often results in suboptimal quality, highlighting a significant opportunity for enhancement. In the realm of conventional CMOS design, post-layout optimization techniques are employed to capitalize on this potential, yet such methods for FCN are either not scalable or lack efficiency. This work bridges this gap by introducing the first scalable and efficient post-layout optimization algorithm for FCN. Experimental evaluations demonstrate the efficiency of this approach: when applied to layouts obtained by a state-of-the-art heuristic method, the proposed post-layout optimization achieves area reductions of up to <inline-formula> <tex-math>$ {mathrm {73.75~%}}~({mathrm {45.58~%}}$ </tex-math></inline-formula> on average). This significant improvement underscores the transformative potential of post-layout optimization in FCN. Moreover, unlike existing algorithms, the method exhibits scalability even in optimizing layouts with over 20 million tiles. Implementations of the proposed methods are publicly available as part of the Munich Nanotech Toolkit (MNT) at <uri>https://github.com/cda-tum/fiction</uri>.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3790-3803"},"PeriodicalIF":2.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10916761","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning 基于多模态学习的优化感知预路由时间预测框架

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-03-04 DOI: 10.1109/TCAD.2025.3547806

Peng Cao;Yusen Qin;Guoqing He;Wenjie Ding;Xu Cheng;Zhanhua Zhang;Yuyang Ye

{"title":"An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning","authors":"Peng Cao;Yusen Qin;Guoqing He;Wenjie Ding;Xu Cheng;Zhanhua Zhang;Yuyang Ye","doi":"10.1109/TCAD.2025.3547806","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3547806","url":null,"abstract":"Accurate and efficient prerouting timing estimation is particularly crucial during placement to alleviate time-consuming design iterations. Machine-learning (ML)-based methods have been introduced recently to predict the post-routing timing results at placement stage, but most of them neglect the impact of timing optimization during physical design, suffering from accuracy loss due to inconsistent circuit netlist. In this work, an optimization-aware prerouting timing prediction framework based on multimodal learning is proposed to calibrate the timing changes between placement and routing stages, where the local netlist and layout information are extracted by graph neural network (GNN) and convolutional neural network (CNN), respectively, while the global information along the path is further extracted by Transformer network. Based on the predicted post-routing timing results by the proposed framework, timing optimization guidance is generated to enhance traditional design flow with better physical implementation quality. Experimental results demonstrate that for the OpenCores benchmark circuits under TSMC 22nm process, the proposed framework achieves significant correlation and accuracy improvement with an average of 0.9219 in terms of R2 score and 2.12% of mean absolute percentage error (MAPE) as well as an average runtime acceleration of <inline-formula> <tex-math>$645times $ </tex-math></inline-formula> compared with traditional design flow on testing designs. With the timing optimization guidance, significant worst negative slack (WNS) and total negative slack (TNS) improvement are achieved compared with traditional flow after placement and routing, respectively, without noticeable area, power, wire length, and the number of design rule check (DRC) violations increase.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3896-3909"},"PeriodicalIF":2.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0