IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"ReFFT: An Energy-Efficient RRAM-Based FFT Accelerator","authors":"Jianan Wen;Andrea Baroni;Max Uhlmann;Eduardo Perez;Christian Wenger;Milos Krstic","doi":"10.1109/TCAD.2025.3627146","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3627146","url":null,"abstract":"The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while crossbars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this article, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to <inline-formula> <tex-math>$mathbf {4.6times }$ </tex-math></inline-formula> and <inline-formula> <tex-math>$mathbf {19.5 times }$ </tex-math></inline-formula> higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2620-2634"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222081","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully Synthesizable Digital-to-Analog Converter Using Shifting Current Mirror Architecture With Multisegmented Data Weighted Algorithm","authors":"Jiajie Huang;Chao Wang;Ting Zhou;Wangzilu Lu;Yan Liu;Duy Hiu Búi;Yongfu Li","doi":"10.1109/TCAD.2025.3624686","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624686","url":null,"abstract":"This article describes a fully synthesizable digital-to-analog converter (DAC). It is important to develop an automated netlist generation and synthesizable design methodology for mixed-signal circuits. To fill in the scarcity of synthesizable DACs, we propose a multibit full-synthesizable current DAC using a shifting current mirror architecture with a multisegmented data weighted averaging (MSeDWA) mismatch correction algorithm. It provides robustness against process, voltage, and temperature (PVT) variations by means of a programmable bias generator, which suppresses the circuit variations by <inline-formula> <tex-math>$gt 2.7times $ </tex-math></inline-formula>. The use of power-gating standard cells provides a flexible selection of current mirror types, thus achieving a widening of the voltage operation range. Moreover, stage separation and appropriate gain configuration ensure high linearity. With the MSeDWA technique, the total harmonic distortion (THD) is further improved by 7.7 dB. Operating between 14 to 56 MHz, the analog and digital circuits consume 8.64–<inline-formula> <tex-math>$56.64~mu $ </tex-math></inline-formula>W and 217–<inline-formula> <tex-math>$629~mu $ </tex-math></inline-formula>W, respectively. The proposed circuit has demonstrated an excellent energy efficiency of <inline-formula> <tex-math>$0.03~mu $ </tex-math></inline-formula>W/kHz while maintaining a maximum THD of 39.9 dB (1.01%).","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2559-2568"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Broadband DC-Bias Included CSWPL Model for RF Power Transistors","authors":"Enduo Liu;Xiaoqiang Tang;Zhiming Fan;Jialin Cai;Shichang Chen;Kuiwen Xu","doi":"10.1109/TCAD.2025.3624682","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624682","url":null,"abstract":"A new broadband dc-bias included model for radio frequency (RF) power transistors is presented in this article. The proposed method utilizes the canonical sectionwise piecewise linear (CSWPL) model framework in order to incorporate both frequency as well as bias information simultaneously. Detailed descriptions of the fundamental theory of the developed model are provided, along with their validation through experiments. The model is implemented in commercial software and validated using dc and RF tests with measured load-pull data from a 10-W GaN device. In contrast to standard and bias-included CSWPL models, this model can predict transistor behavior under a variety of bias voltages and frequencies using only one set of parameters, thereby significantly reducing model complexity. In addition, the proposed model is applied to a multioctave power amplifier (PA) design to provide further validation. Measurements made on the realized PA are compared with simulations based on the proposed model. Validity of the extracted model is confirmed by the agreement between measurements and simulations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2707-2717"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CD-FiLM: Contrastive Masked Decoder With Feature-Wise Linear Modulation for Power–Signal Integrity Co-Analysis of High-Speed Transmitters","authors":"Songyu Sun;Cheng Zhuo","doi":"10.1109/TCAD.2025.3621408","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3621408","url":null,"abstract":"High-speed serial links are crucial for data transmission in high-performance systems, where increasing data rates demand robust transmitter (TX) performance. Maintaining signal and power integrity (SI/PI) in highly nonlinear TXs is essential, especially as lower power supply levels heighten their sensitivity to power supply noise (PSN). The interaction between PSN and input signals through coupled pathways further complicates PI–SI co-analysis of TXs. In this work, we propose a physics-inspired TX model, a contrastive masked decoder with feature-wise linear modulation (CD-FiLM), for PI–SI co-analysis of high-speed TXs. We identify that the input and output features of the circuit correspond to different modalities under the same circuit state. By incorporating contrastive learning into a supervised learning framework, CD-FiLM aligns input and output to the same circuit state space, enhancing robust feature representations and thus improving the accuracy of noisy output signal predictions. We design an effective feature fusion module that captures signal and circuit interactions by modulating the input and PSN signals with circuit parameters, forming a comprehensive circuit state representation. To efficiently capture the temporal dependencies within the highly nonlinear TX output signals, we use masked data modeling (MDM) for structural learning of long-sequence signals, employing a masked decoder for efficient parallel decoding. Experimental results show that CD-FiLM achieves efficient PI–SI co-analysis for TXs in high-speed links operating up to hundreds of GHz, producing eye diagrams with mean relative errors of 0.10%–2.24% and 100–<inline-formula> <tex-math>$134times $ </tex-math></inline-formula> speedup.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2787-2798"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs","authors":"Junqi Chen;Chubo Liu;Peiying Lin;Zheng Xiao;Youquan Chang;Zhuo Tang;Kenli Li","doi":"10.1109/TCAD.2025.3620248","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3620248","url":null,"abstract":"As integrated circuit design continues to scale, 3-D integrated circuit (3D-IC) technology has emerged as a promising solution to extend Moore’s law. Among various physical design stages, placement plays a pivotal role, directly influencing key power, performance, and area (PPA) metrics. In research that does not consider specific 3DIC process technologies, the state-of-the-art ePlace-3-D introduces 3-D electrostatic field density modeling, enabling nonlinear placement algorithms to truly address 3-D placement problems. However, its complex flow results in low runtime efficiency. In this work, we propose LightPlace, a lightweight and effective 3-D placement framework. This framework incorporates the virtual macro insertion approach and the macro connection reconstruction method, which streamlines the macro placement phase and allocates space for subsequent standard cell placement. These innovations enhance runtime efficiency and optimize wirelength. Experimental results on the large-scale modern mixed-size (MMS) benchmarks demonstrate that LightPlace reduces total wirelength by an average of 10% and achieves up to <inline-formula> <tex-math>$4times $ </tex-math></inline-formula> faster runtime compared to the runtime reported for ePlace-3D.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2546-2558"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Layout Synthesis of RRAM Array With Minimized Proximity Effect","authors":"Yuhang Zhang;Guanghui He;Guoxing Wang;Yongfu Li","doi":"10.1109/TCAD.2025.3625102","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3625102","url":null,"abstract":"The lithography process inherently introduces device-to-device variation in the fabrication of resistive random access memory (RRAM) arrays, introducing electrical mismatch and limiting the practical applications of RRAM-based analog computing circuits. In this work, we propose a lithography model-aware layout synthesis framework to minimize the proximity effect in the lithography process, thus reducing the electrical mismatch among these devices for analog computing applications. A dummy RRAM cell insertion technique is proposed to reduce the geometrical mismatch among RRAM cells, and a bi-objective alternate optimization method is proposed to efficiently optimize the geometric parameters and the structure of RRAM layouts. In addition, an approximation method for evaluating the quality of the RRAM array layout is proposed to reduce the runtime of synthesis. The experimental results show that our proposed framework significantly reduces the deviation between printed and expected patterns.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2611-2619"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring “Many in Few” and “Few in Many” Properties in Long-Tailed, Highly Imbalanced IC Defect Classification","authors":"Hao-Chiang Shao;Chun-Hao Chang;Yu-Hsien Lin;Chia-Wen Lin;Shao-Yun Fang;Yan-Hsiu Liu","doi":"10.1109/TCAD.2025.3625105","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3625105","url":null,"abstract":"Despite significant advancements in deep classification techniques and in-laboratory automated optical inspection (AOI) models for long-tailed or highly imbalanced data, applying these approaches to real-world IC defect classification tasks remains challenging. This difficulty stems from two primary factors. First, real-world conditions, such as the high yield-rate requirements in the IC industry, result in data distributions that are far more skewed than those found in general public imbalanced datasets. Consequently, classifiers designed for open imbalanced datasets often fail to perform effectively in real-world scenarios. Second, real-world samples exhibit a mix of class-specific attributes (e.g., defect types) and class-agnostic, domain-related features (e.g., design characteristics of product lines). This complexity adds significant difficulty to the classification process, particularly for highly imbalanced datasets. To address these challenges, this article introduces the IC-Defect-14 dataset, a large, highly imbalanced IC defect image dataset sourced from AOI systems deployed in real-world IC production lines. This dataset is characterized by its unique “intraclass clusters” property, which presents two major challenges: large intraclass diversity and high interclass similarity. These characteristics, rarely found simultaneously in existing public datasets, significantly degrade the performance of current state-of-the-art (SOTA) classifiers for highly imbalanced data. To tackle this challenge, we propose the regional channel attention-based multiexpert network (ReCAME-Net). This network follows a multiexpert classifier framework and integrates a regional channel attention module, metric learning losses, a hard category mining strategy, and a knowledge distillation procedure. Extensive experimental evaluations demonstrate that ReCAME-Net outperforms previous SOTA models on the IC-Defect-14 dataset while maintaining comparable performance and competitiveness on general public datasets. Our resources can be found at <uri>https://github.com/YoursEver/ReCAME–Net</uri>","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2813-2825"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LiDAR 2.0: Hierarchical Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits","authors":"Hongjian Zhou;Haoyu Yang;Ziang Yin;Nicholas Gangi;Zhaoran Huang;Haoxing Ren;Joaquin Matres;Jiaqi Gu","doi":"10.1109/TCAD.2025.3624197","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624197","url":null,"abstract":"Driven by innovations in photonic computing and interconnects, photonic integrated circuit (PIC) designs advance and grow in complexity. Traditional manual physical design processes have become increasingly cumbersome. Available PIC layout tools are mostly schematic-driven, which has not alleviated the burden of manual waveguide planning and layout drawing. Previous research in PIC automated routing is largely adapted from electronic design, focusing on high-level planning and overlooking photonic-specific constraints such as curvy waveguides, bending, and port alignment. As a result, they fail to scale and cannot generate DRV-free layouts, highlighting the need for dedicated electronic–photonic design automation (EPDA) tools to streamline PIC physical design. In this work, we present <monospace>LiDAR</monospace>, the first automated PIC detailed router for large-scale designs. It features a grid-based, curvy-aware A<inline-formula> <tex-math>${}^{ast }$ </tex-math></inline-formula> engine with adaptive crossing insertion, congestion-aware net ordering, and insertion-loss optimization. To enable routing in more compact and complex designs, we further extend our router to hierarchical routing as <monospace>LiDAR</monospace> 2.0. It introduces redundant-bend elimination, crossing-space preservation, and routing order refinement for improved conflict resilience. We also develop and open-source a YAML-based PIC intermediate representation (PIC IR) and diverse benchmarks, including TeMPO, GWOR, and Bennes, which feature hierarchical structures and high crossing densities. Evaluations across various benchmarks show that <monospace>LiDAR</monospace> 2.0 produces nearly DRV-free layouts, achieving up to 16% lower insertion loss (IL) and <inline-formula> <tex-math>$7.69times $ </tex-math></inline-formula> speedup over prior methods on spacious cases, and 9% lower IL with <inline-formula> <tex-math>$6.95times $ </tex-math></inline-formula> speedup over LiDAR 1.0 on compact cases. Our codes are open-sourced at <uri>https://github.com/ScopeX-ASU/LiDAR</uri>","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2664-2678"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multiscenario Coupled Model of GaN-on-Si HEMTs Epitaxial Design and Performance Improvement Based on Multiobjective Optimization Method","authors":"Borui Deng;Yulong Fang;He Guan;Ziqiang Zeng;Yongchuan Tang;Ying Wang","doi":"10.1109/TCAD.2025.3624685","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624685","url":null,"abstract":"Gallium nitride high-electron mobility transistors (GaN-on-Si HEMTs) on silicon substrates exhibit significant potential in the field of radio frequency devices due to its high frequency, high-speed, and low-cost advantages. Nevertheless, the thermal stress caused by the mismatch in lattice parameters and the coefficient of thermal expansion between the Si substrate and GaN epitaxial layer constrains the device performance. Due to different temperature distributions in different scenarios, there is an urgent need for a model that can balance the contradiction between epitaxial growth and device operation for the joint design of GaN-on-Si HEMTs’ epitaxial structures. This work presents thermal stress formulas specifically designed for GaN epitaxial growth and device operation, based on Townsend’s theory of multilayer film curvature and stress. Furthermore, our work innovatively proposes a multiscenario coupled GaN-on-Si HEMTs’ epitaxial structure design model based on multiobjective optimization. The model represents a combined objective function incorporating thermal stress experienced during device operation and epitaxial growth, as well as the total thermal resistance and bulk thermal conductivity of the epitaxial layer. Through simulation validation, the model has been proved to effectively calculate the optimized epitaxial structure parameters across multiple scenarios to meet diverse requirements. And it can effectively reduce the operating temperature. This model can accelerate the process of GaN epitaxial design and provide an effective method for enhancing the performance of GaN-on-Si HEMTs.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2718-2724"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analog Mixed-Signal Circuit Splitting and Defect Simulation Method Based on Signal Flow Diagram","authors":"Chenglin Yang;Hanyu Wen;Xinhong Huang;Han Chen;Qihao Zhang;Haitao Fu","doi":"10.1109/TCAD.2025.3624276","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3624276","url":null,"abstract":"Comprehensive defect simulation in the integrated circuit design stage is the basic guarantee to improve testability, which is also the basic requirement of current automotive-grade chip design. For example, there are six types of basic defect models for a single MOS transistor in a circuit, and the defect set of analog/hybrid integrated circuits containing thousands of devices is extremely large. It is very time-consuming to inject a large number of defects one by one and solve them in a large-scale matrix. In fact, the complete defect simulation often takes months or even years, and there is no good solution at present. In this article, a circuit splitting method based on signal flow and graph analysis is proposed, which models the control relationship between the device current and voltage nodes of the circuit with a directed dependence graph (DDG) through signal flow analysis. Then, more weak connections are obtained by identifying and breaking the feedback loops of larger strongly connected components (SCCs), and the weak connectivity in SCCs is split to realize circuit splitting. The acceleration can then be achieved by parallel defect simulation. At the same time, in order to investigate the observability of the internal defects in the previous SCCs in the subsequent SCCs, the defects were simulated according to the one-way transfer relationship between each SCC in a directed acyclic graph (DAG). An equivalent compression method of the defects and the signal in the transfer process is proposed, which reduces the number of simulation times of the defects. Finally, this article takes the benchmark BANDGAP, LDO, and SARADC circuits as examples and uses HSPICE simulation to verify the effectiveness of the graph splitting method. Compared with the latest transistor-level circuit splitting scheme, the circuit splitting algorithm proposed in this article can split more and smaller circuit blocks. Using the circuit blocks, we have divided to implement the parallel defect simulation scheme, and the defect transfer simulation scheme is more effective than the traditional full-circuit and full-defect simulation one by one.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2739-2752"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}