NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash

IF 2.9 3区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-02-25 DOI:10.1109/TCAD.2025.3545362

Qianqi Zhao;Jing He;Tong Qu;Wentian Wu;Qianhui Li;Qi Wang;Zongliang Huo;Tianchun Ye

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引用次数: 0

Abstract

Quad-level cell (QLC) has received significant attention recently due to its extremely high storage capacity. However, because of its poor reliability, QLC-based solid-state drives (SSDs) require a two-step programming to reduce the layer interference. But during the interval between two programming steps on the same wordline (WL), data could be invalidated from update operations, leading to invalid programming and degraded performance. To mitigate the performance loss, we propose the NV-APP scheme to minimize the program and verify pulses during the second-step programming. NV-APP integrates the no-verify (NV) scheme and the adaptive pulse programming scheme (APP). The NV scheme omits verify pulses of invalid verify voltages. The APP scheme adaptively increases the programming step voltage

$(V_{\mathrm { step}})$

to accelerate cells’ threshold voltage shift, reducing the number of both program and verify pulses. Device-level simulation results show that the NV-APP scheme reduces the total number of program pulses by an average of 27.03% and verify pulses by an average of 48.70% across various invalid cases during the second-step programming. Based on a modified 3-D QLC SSD simulator with typical traces, the experiments demonstrate that our scheme reduces two-step programming time by an average of 17% on partially invalid WLs, close to the 19.8% reduction achieved by the ideal scheme with no performance loss.

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NV-APP：三维QLC闪存的无效编程性能改进无验证和自适应脉冲编程方案

四能级电池（QLC）由于其极高的存储容量，近年来受到了广泛的关注。然而，由于可靠性差，基于qlc的固态硬盘（ssd）需要两步编程来减少层间干扰。但是在同一字行（WL）上的两个编程步骤之间的间隔期间，更新操作可能会使数据无效，从而导致无效的编程和性能下降。为了减少性能损失，我们提出了NV-APP方案来最小化程序，并在第二步编程时验证脉冲。NV-APP集成了NV （no-verify）方案和APP （adaptive pulse programming）方案。NV方案省略了无效验证电压的验证脉冲。APP方案自适应地增加编程阶跃电压$(V_{\mathrm {step}})$，加速单元的阈值电压偏移，减少程序和验证脉冲的数量。器件级仿真结果表明，在第二步编程过程中，NV-APP方案在各种无效情况下平均减少了27.03%的程序脉冲总数，平均减少了48.70%的验证脉冲。在一个具有典型迹线的改进的三维QLC固态硬盘模拟器上，实验表明，我们的方案在部分无效的WLs上平均减少了17%的两步编程时间，接近理想方案在没有性能损失的情况下减少19.8%的编程时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 工程技术-工程：电子与电气

CiteScore

5.60

自引率

13.80%

发文量

500

审稿时长

7 months

期刊介绍： The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.