IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"A Framework for Dynamic Quantum Circuit Execution: Balancing Effectiveness and Efficiency","authors":"Fangzheng Chen;Hao Fu;Mingzheng Zhu;Chi Zhang;Wei Xie;Xiang-Yang Li","doi":"10.1109/TCAD.2025.3626447","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3626447","url":null,"abstract":"Quantum computing has exhibited remarkable advancements in recent years. On superconducting quantum chips, physical qubits are interconnected with limited coupling topologies. Since two-qubit gates can only be operated between adjacent qubits, quantum circuits must undergo transformation to satisfy these connectivity constraints—a process known as qubit mapping and routing. Dynamic quantum circuits represent a critical paradigm in quantum computing, which features mid-circuit measurements and conditional control flows (controlled subcircuits) based on measurement outcomes. A distinctive challenge arises when controlled subcircuits are determined only after measurement results become available (online acquisition). Thus, mapping and routing dynamic quantum circuits presents complex challenges, including managing the conditional execution of controlled subcircuits, accommodating their online/offline acquisitions, and resolving mapping misalignments between circuit segments. In this work, we propose a comprehensive framework for transforming and executing dynamic quantum circuits. In this framework, we present a mapping and routing algorithm <monospace>Sword</monospace> that effectively reduces the quantum processing time of quantum circuits, which applies SWAP(s) with occupancy and gate regional density. For online scenarios, we introduce a fast variant <monospace>Sword-fast</monospace> that significantly improves transformation efficiency with negligible performance degradation. Experimental evaluations demonstrate that our framework achieves an average 37.1% reduction in end-to-end wall-clock time compared with baseline approaches for offline scenarios. In online scenarios, our framework achieves 59.2% average reduction of end-to-end wall-clock time, demonstrating <inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula> average speedup in transformation time and 30.0% average reduction in quantum processing time. By replacing the qubit mapping and routing algorithm in our framework with a fast variant, <monospace>Sword-fast</monospace>, we achieve a <inline-formula> <tex-math>$9.6times $ </tex-math></inline-formula> average speedup in transformation time compared with the standard version.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2583-2596"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PIMapping: A Tile-Level Dataflow Optimization Framework for PIM Architecture","authors":"Ziqian Zhu;Yifei Zhou;Jinsen Zhu;Yuxuan Wang;Hongbing Pan","doi":"10.1109/TCAD.2025.3621513","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3621513","url":null,"abstract":"Process-in-memory (PIM) accelerators demonstrate outstanding performance in accelerating matrix-vector multiplication (MVM) tasks in neural networks. To achieve better acceleration performance, extensive research has focused on the design of hierarchical tile-based PIM architectures, presenting challenges for the hardware deployment of algorithms. Multilayer parallelism in tile-based architectures requires the support of dataflow optimization techniques. However, existing research primarily performs dataflow analysis using computational models and performance metrics that are not suitable for tile-level dataflows. In this article, we propose an analytical framework, PIMapping, for tile-based PIM architectures that supports multilayer parallelism mapping and tile-level dataflow optimization. In this work, we first establish a general dataflow representation for tile-level dataflow, which serves as an intermediate representation (IR) for multilayer DNN mapping and scheduling tasks at the tile level. Next, based on the proposed representation, we introduce a data proximity-based mapping method aimed at minimizing the intertile communication overhead. Furthermore, we propose a congestion-aware scheduling algorithm to minimize intertile communication conflicts. Experimental case studies are conducted to map common DNN algorithms onto different PIM architectures. The results demonstrate significant improvements over the state-of-the-art mapping framework in terms of communication latency, required intertile bandwidth, and pipeline efficiency.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2569-2582"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approximation Methods for Simulation and Equivalence Checking of Noisy Quantum Circuits","authors":"Mingyu Huang;Ji Guan;Wang Fang;Mingsheng Ying","doi":"10.1109/TCAD.2025.3623498","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3623498","url":null,"abstract":"In the current noisy intermediate-scale quantum (NISQ) era, simulating and verifying noisy quantum circuits is crucial but faces challenges such as quantum state explosion and complex noise representations, constraining simulation and equivalence checking to circuits with a limited number of qubits. This article introduces an approximation algorithm for simulating and assessing the equivalence of noisy quantum circuits, specifically designed to improve scalability under low-noise conditions. The approach utilizes a novel tensor network (TN) diagram combined with singular value decomposition to approximate the tensors of quantum noises. The implementation is based on Google’s TensorNetwork Python package for contraction. Experimental results on realistic quantum circuits with realistic hardware noise models indicate that our algorithm can simulate and check the equivalence of quantum approximate optimization algorithm (QAOA) circuits with around 200 qubits and 20 noise operators, outperforming state-of-the-art approaches in scalability and speed.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 6","pages":"2679-2692"},"PeriodicalIF":3.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-Enhanced Genetic Algorithm-Based Approach","authors":"Yi-Ting Li;Ihao Chen;Yung-Chih Chen;Chun-Yao Wang","doi":"10.1109/TCAD.2025.3603509","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3603509","url":null,"abstract":"This article presents a novel approach to approximate logic synthesis (ALS) targeting at Dot-Inverter Graph (DIG), which is known for its superior expressive ability among all three-input gates and its potential in the future technology. We focus on minimizing the size of DIG circuits while maintaining acceptable error rates (ERs) by introducing a node merging (NM)-enhanced genetic algorithm (GA)-based approach. The NM technique reduces the DIG size without altering its functionality, while the GA, incorporating average relative Hamming distance (ARHD) and a self-adjusted mutation level (ML), is used for ALS on DIGs. Our experimental results demonstrated that the proposed approach achieves a higher reduction rate and less CPU time on different sizes of circuits compared to the state-of-the-art ALS approach.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1732-1745"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient FRW Transitions via Stochastic Finite Differences for Handling Non-Stratified Dielectrics","authors":"Jiechen Huang;Wenjian Yu","doi":"10.1109/TCAD.2025.3602737","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3602737","url":null,"abstract":"The accuracy of floating-random-walk (FRW)-based capacitance extraction stands only when the recursive FRW transitions are sampled unbiasedly according to surrounding dielectrics. Advanced technology profiles, featuring complicated nonstratified dielectrics, challenge the accuracy of existing FRW transition schemes that approximate dielectrics with stratified or eight-octant patterns. In this work, we propose an algorithm named MicroWalk, enabling accurate FRW transitions for arbitrary dielectrics while keeping high efficiency. It is provably unbiased and equivalent to using transition probabilities solved by finite difference method (FDM), but at orders of magnitude lower cost (<inline-formula> <tex-math>$802times $ </tex-math></inline-formula> faster). An enhanced 3-D capacitance solver is developed with a hybrid strategy for complicated dielectrics, combining MicroWalk with the special treatment for the first transition cube and the analytical algorithm for stratified cubes. Experiments on real-world structures show that our solver achieves a significant accuracy advantage over existing FRW solvers, while preserving high efficiency.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1746-1750"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"NFGen: Normalizing Flow-Based Joint Generative Model for Variability-Aware Design Technology Co-Optimization","authors":"Tao Zou;Zhenxing Dou;Zhiwei Chen;Yijiao Wang;Wen Shi;Zhiyu Wang;Peng Wang;Runsheng Wang;Weisheng Zhao;Asen Asenov","doi":"10.1109/TCAD.2025.3604349","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3604349","url":null,"abstract":"As transistor sizes continue shrinking, the impacts of variability have become ever more paramount in circuit design and manufacturing. Their accurate representations in model cards help save design margins and provide appropriate guidelines in design technology co-optimization (DTCO). To address such a challenge, we propose a novel machine learning framework, normalizing flow-based joint generative (NFGen) model, which generates a comprehensive model library from a limited number of model cards. Unlike traditional generative methods that focus on the marginal distribution of model card parameters, NFGen is the first model to approximate their joint distribution, which includes information on their correlation and thus enables closer representation of variability effects. In addition, we introduce two similarity metrics to rigorously evaluate the quality of generated model cards. Experimental results show that NFGen reduces overall error by <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> compared to state-of-the-art methods, validating its superiority in variability-aware DTCO.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1764-1768"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture","authors":"Pengyu Liu;Liyan Chen;Zelong Yuan;Yingkun Liu;Jianfei Jiang;Qin Wang;Zhigang Mao;Naifeng Jing","doi":"10.1109/TCAD.2025.3607137","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607137","url":null,"abstract":"While 3D-stacked static random-access memory (SRAM) architectures have demonstrated prominent performance speedup for tensor computing by exploiting higher bandwidth, larger buffer, and reduced latency, they suffer from thermal challenges owing to the vertical stacking nature of chips. In this article, we identify that tensor dataflow may further exacerbate the thermal issues, so we propose T3D, the first thermal-aware tensor framework for 3D-stacked SRAM architectures, leveraging tensor dataflow characteristics to significantly enhance thermal performance. Specifically, we first perform a quantitative formulation to identify the most energy-efficient tensor dataflow with given 3-D constraints, effectively reducing heat generation without performance loss. Then, we develop a thermal-aware 3-D architectural floor plan to improve heat spreading by optimizing the spatial arrangement of multiple SRAM macros with varying power overheads, which is caused by mismatched data access rates of tensor computing. Experimental results show that our proposed T3D can reduce the peak chip temperature by <inline-formula> <tex-math>$12.9~^{circ }$ </tex-math></inline-formula>C on certain LLM and DNN workloads over the state-of-the-art 3-D solutions.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1598-1610"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Layer-Constrained GNR Area Routing With CNT-Via Insertion for Via Minimization","authors":"Jin-Tai Yan;Chia-Heng Yen","doi":"10.1109/TCAD.2025.3604646","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3604646","url":null,"abstract":"It is known that graphene nanoribbon (GNR) can be used as interconnects in nanoscale designs. To reduce the manufacturing cost in GNR routing, the constraint on the number of used layers becomes more important. In this article, given a set of GNR nets on a constrained set of routing layers inside a limited area, based on the concept of using GNR wires with CNT-via insertion in GNR routing, an efficient routing algorithm can be proposed to maximize the routability of the GNR nets and minimize the total wirelength in assignment of the feasible routed paths while satisfying the noncrossing constraint on the GNR nets. First, based on the construction of a crossing graph on the length-oriented consideration of the multiple-pin nets, all the intervals representing the GNR nets with covering compatibility can be assigned to the minimized tracks, and the represented intervals on the extra tracks can be reassigned to the constrained tracks by using two separation-and-reassignment operations. Furthermore, based on the assignment result of the represented intervals on the constrained tracks and the hierarchical covering tree of the independent nets and the separated subnets on the constrained layers, the full and partial boundary-oriented paths of the GNR nets can be assigned on the constrained layers for routability, and the assigned paths of the GNR nets can be modified to reduce the number of used bends and the total wirelength of the GNR nets. Compared with the combination of Yen’s routing algorithm and the rip-up and reroute (RAR) process in layer-constrained GNR area routing with CNT-via insertion, the proposed algorithm can increase 2.1% of routability for 12 tested examples under 24 different constraints on average. In addition, the proposed algorithm can reduce 31.6% of the number of inserted CNT-vias, 5.5% of the number of used bends, and 2.3% of the total wirelength for 12 tested examples under 13 different constraints with 100% routability on average.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1677-1690"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Algorithm for Exact SRAM Verification via Novel Pattern-Matching Techniques","authors":"Sunkanghong Wang;Qingsheng Qiu;Hao Zhang;Lijun Wei;Qiang Liu","doi":"10.1109/TCAD.2025.3602734","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3602734","url":null,"abstract":"As semiconductor manufacturing advances into ultrascaled technology nodes, static random access memory (SRAM) verification faces critical challenges stemming from increasingly stringent geometries, heightened process variability, and the sheer density of contemporary designs. Existing methodologies, notably design rule checking (DRC) and conventional pattern matching, often fall short in capturing the intricate multilayer interactions and subtle geometric deviation characteristic of advanced SRAM layouts. These limitations can lead to missed layout anomalies and potential functional failures, resulting in diminished yield. This article introduces a specialized pattern-matching-based algorithm designed to address these challenges in SRAM verification. The algorithm integrates novel localization techniques, efficient spatial indexing, and an overlap detection procedure that together achieve exact verification while delivering substantial improvements in runtime performance. The experimental results confirm that this approach not only maintains 100% detection accuracy on complex SRAM benchmarks, but also achieves speedups ranging from threefold to over 20-fold compared to state-of-the-art methods, and from twofold to several thousandfold on classic single-layer pattern-matching datasets.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1827-1840"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM With Self-Assembled Bitcell Units and MILP-Based Optimization","authors":"Chuyu Wang;Xinglong Yan;Zecheng Xu;Ke Hu;Keren Zhu;Shuo Li;Fan Yang;Xuan Zeng","doi":"10.1109/TCAD.2025.3608064","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3608064","url":null,"abstract":"Digital computing-in-memory (DCIM) systems integrate complex digital logic with parasitic-sensitive bitcell arrays, presenting unique physical design challenges. Conventional design strategies often fall short in these systems due to irregular dataflow patterns and excessive interconnect lengths, which degrade performance and increase parasitic effects. As a result, current DCIM implementations frequently rely on manual layout, which is both time-consuming and a major bottleneck in the design cycle. While existing DCIM layout synthesis frameworks attempt to automate this process using template-based placement methods inspired by manual design, their rigid constraints can lead to inefficient area utilization and increased core sizes. To address these limitations, we propose DAMIL-DCIM+, a novel placement framework that combines the structural clarity of template-based methods with the flexibility of optimization-based techniques. Specifically, DAMIL-DCIM+ employs a global dataflow-aware floorplan to guide placement and leverages MILP-based detailed placement to optimize wirelength and preserve dataflow regularity. Inspired by self-assembling design principles, this approach enables scalable and structured integration of parasitic-sensitive components. The hybrid methodology of DAMIL-DCIM+ reduces total wirelength, lowers parasitic effects, and enhances performance while maintaining design regularity. Experimental results on a 28-nm DCIM circuit demonstrate that DAMIL-DCIM+ improves operating frequency by 25.2% and reduces power consumption by 19.6% compared to Cadence Innovus, without increasing core area.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1691-1703"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}