COCO:基于配置的压缩测试集的压缩

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Irith Pomeranz
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引用次数: 0

摘要

全面的缺陷覆盖需要从几个故障模型中检测故障的测试集。通常对测试集进行封顶,以检测来自尚未检测到的附加故障模型的故障。这将创建大型测试集,其最后的测试检测少量附加故障。减少已满测试集(或具有大量故障的故障模型的测试集)的存储需求是本文的主题。前面已经说明,可以通过补充单个比特,从先前出现的测试生成测试集的最后测试,而不是完整地存储最后的测试。当只存储互补位时,减少了存储需求;但是,应用测试的数量增加了。本文观察到,通过更改将解压的测试数据转移到扫描链中的配置,可以产生新的测试,这些测试可以有效地替换已完成测试集末尾的测试,而不会增加应用测试的数量。本文在学术环境中开发了该方法,并使用学术软件工具实现了该方法。将其应用于基准电路,验证了其有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set
Comprehensive defect coverage requires test sets that detect faults from several fault models. A test set is typically topped-off to detect faults from an additional fault model that are not already detected. This creates large test sets whose last tests detect small numbers of additional faults. Reducing the storage requirements of topped-off test sets (or test sets for fault models with large numbers of faults) is the topic of this article. Instead of storing the last tests in their entirety, it was shown previously that it is possible to produce the last tests of the test set from tests that appear earlier by complementing single bits. The storage requirements are reduced when only complemented bits are stored; however, the number of applied tests is increased. This article observes that changing the configuration by which decompressed test data are shifted into scan chains produces new tests that are effective in replacing tests at the end of a topped-off test set without increasing the number of applied tests. This approach is developed in this article in an academic environment and implemented using academic software tools. It is applied to benchmark circuits to demonstrate its effectiveness.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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