延迟驱动的直角斯坦纳树构造

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Hongxi Wu;Xingquan Li;Liang Chen;Bei Yu;Wenxing Zhu
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引用次数: 0

摘要

时序驱动路由在复杂电路设计中至关重要。现有的浅光斯泰纳树构建方法在导线长度(WL)和源-汇路径长度(PL)之间取得了平衡,但在延迟方面存在不足。相反,以前的延迟驱动方法优先考虑延迟,但会导致更长的 WL 和 PL,从而使其成为次优方法。在本文中,我们证明了同时缩短 WL 和 PL 可以有效减少延迟。此外,我们还研究了在减少 PL 的过程中延迟是如何变化的。在理论发现的指导下,我们开发了一种直线浅光斯坦纳树构建算法,旨在减少延迟的同时保持有界的 WL。此外,我们还提出了一种延迟驱动的边缘移动算法,用于微调树的拓扑结构,进一步减少延迟。我们的研究表明,我们提出的边缘移动算法在重复应用时可以返回局部帕累托最优解。实验结果表明,与之前的方法相比,我们的算法实现了最低的总延迟,同时保持了有竞争力的 WL。此外,对于具有时序信息的引脚网络,我们的算法可以根据时序信息生成最合适的斯坦纳树。此外,扩展实验强调了构建总延迟最小的直线斯坦纳树的积极影响。我们的代码将发布在 https://github.com/Whx97/Delay-driven-Steiner-Tree 网站上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Delay-Driven Rectilinear Steiner Tree Construction
Timing-driven routing is crucial in complex circuit design. Existing shallow-light Steiner tree construction methods balance between wire length (WL) and source-sink path length (PL) but lack in delay. Conversely, previous delay-driven methods prioritize delay but result in longer WL and PL, making them suboptimal. In this article, we show that simultaneously reducing the WL and PL can effectively reduce the delay. Furthermore, we investigate how delay changes during the reduction of PL. Guided by the theoretical findings, we develop a rectilinear shallow-light Steiner tree construction algorithm designed to reduce delay meanwhile maintaining a bounded WL. Furthermore, a delay-driven edge shifting algorithm is proposed to fine tune the tree’s topology, further reducing delay. We show that our proposed edge shifting algorithm can return a local Pareto optimal solution when repeatedly applied. Experimental results show that our algorithm achieves the lowest total delay compared to previous methods while maintaining competitive WL. Moreover, for nets with pins that have timing information, our algorithm can generate the most suitable Steiner Tree based on the timing information. In addition, extended experiments highlight the positive impact of constructing rectilinear Steiner trees with minimized total delay. Our codes will be available at https://github.com/Whx97/Delay-driven-Steiner-Tree.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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