IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献_第10页

A High-Area-Efficiency Computing-in-Memory Deep Learning Accelerator Based on Weight-Sparsity Activation Compression and Sparsity Reciprocity 基于权重稀疏激活压缩和稀疏互易的高效内存深度学习加速器

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-08-19 DOI: 10.1109/TCAD.2025.3600576

Chu-Yao Lee;Chih-Cheng Lu;Meng-Fan Chang;Kea-Tiong Tang

{"title":"A High-Area-Efficiency Computing-in-Memory Deep Learning Accelerator Based on Weight-Sparsity Activation Compression and Sparsity Reciprocity","authors":"Chu-Yao Lee;Chih-Cheng Lu;Meng-Fan Chang;Kea-Tiong Tang","doi":"10.1109/TCAD.2025.3600576","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3600576","url":null,"abstract":"The large number of parameters in deep neural networks (DNNs) poses significant challenges for resource-constrained hardware. To address this, researchers have focused on model sparsity to skip redundant computations and improve inference speed and computing-in-memory (CIM) techniques to reduce data transfer delays and lower energy consumption. However, leveraging activation sparsity within CIM macros remains challenging due to its architectural limitations, leading to bottlenecks in this research direction. This study proposes an activation compression method based on the CIM structure and weight sparsity, along with a new approach called sparse reciprocity, to enhance model sparsity. A high-area-efficiency CIM-based accelerator chip was developed using these techniques and prior expertise. Experiments on various models and data precisions demonstrate an activation compression ratio of up to 54%, with the proposed accelerator achieving an area efficiency of 243 GOPS/mm2 for the VGG16 model and 363 GOPS/mm2 for the ResNet18 model.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1366-1370"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CATCH: A Cost Analysis Tool for Co-Optimization of Chiplet-Based Heterogeneous Systems CATCH：基于芯片的异构系统协同优化的成本分析工具

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-08-11 DOI: 10.1109/TCAD.2025.3597570

Alexander Graening;Jonti Talukdar;Saptadeep Pal;Krishnendu Chakrabarty;Puneet Gupta

{"title":"CATCH: A Cost Analysis Tool for Co-Optimization of Chiplet-Based Heterogeneous Systems","authors":"Alexander Graening;Jonti Talukdar;Saptadeep Pal;Krishnendu Chakrabarty;Puneet Gupta","doi":"10.1109/TCAD.2025.3597570","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3597570","url":null,"abstract":"With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to a single die per package, now there are viable 3-D stacking options to integrate multiple dies in a package either through vertical stacking or horizontal integration on a substrate along with a plethora of choices regarding configurations and processes. For chiplet-based designs, high-impact decisions, such as those regarding the number of chiplets, the design partitions, the interconnect types, and other factors must be made early in the development process. In this work, we describe an open-source tool, CATCH, that can be used to guide these early design choices. We also present case studies showing some of the insights we can draw by using this tool. We look at case studies on optimal chip size, defect density, test cost, IO types, assembly processes, and substrates. Additionally, we include the cost breakdown for a specific case based on a prior work.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1091-1104"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced LDPC Coding for 3-D TLC NAND Flash Memory: Leveraging RBER Difference From Intralayer Variation 三维TLC NAND闪存的增强LDPC编码：利用层内变化的RBER差异

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-08-14 DOI: 10.1109/TCAD.2025.3598931

Lanlan Cui;Fei Wu;Meng Zhang;Zhanzhan Zhao;Xuan Zhang;Kun Jiang;Changsheng Xie

{"title":"Enhanced LDPC Coding for 3-D TLC NAND Flash Memory: Leveraging RBER Difference From Intralayer Variation","authors":"Lanlan Cui;Fei Wu;Meng Zhang;Zhanzhan Zhao;Xuan Zhang;Kun Jiang;Changsheng Xie","doi":"10.1109/TCAD.2025.3598931","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3598931","url":null,"abstract":"NAND flash memory employs high code rate low-density parity-check (LDPC) codes to reduce the amount of redundant data that must be added. When the code rate is high, although the redundancy space is small, the error correction capability is inferior to medium or low code rate LDPC. raw bit error rate (RBER) varies among the storage layers for 3-D triple-level cell (TLC) NAND flash memory, which increases the frequency of read retry operations. Repeatedly initiating read retry seriously increases the decoding latency and decreases the performance of the 3-D TLC NAND flash memory. To alleviate this problem, this article proposes IntraLayer Variation aware LDPC coding, called LVLDPC. The proposed LVLDPC scheme establishes the correlation between interlayer interference and RBER based on a neural network model. By analyzing and predicting RBER through the neural network model, we are able to categorize RBER into distinct levels. Then, we then select LDPC codes with appropriate error correction capabilities to decode data with varying levels of RBER. Through this scheme, we do not need to start read retry when RBER <inline-formula> <tex-math>$ lt 1.56 times {10^{ - 2}} $ </tex-math></inline-formula>. The iteration number is reduced by 67% in total. This scheme only causes 1.15% space overhead, which is negligible. For the stage with high RBER, the number of iterations of LVLDPC is still large, and the extended LVLDPC scheme (eLVLDPC) is further proposed to reduce the use of high code rate and reduce the number of iterations by 19.1%, expanding the correctable RBER threshold to <inline-formula> <tex-math>$ 2.68 times {10^{ - 2}} $ </tex-math></inline-formula>.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1251-1261"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fraggle: Reducing File Fragmentation on DRAM-Less SSD Fraggle：减少ram - less SSD上的文件碎片

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-08-26 DOI: 10.1109/TCAD.2025.3602747

Weizhou Huang;Hepei Wu;Shuhan Bai;Jian Zhou;Fei Wu

{"title":"Fraggle: Reducing File Fragmentation on DRAM-Less SSD","authors":"Weizhou Huang;Hepei Wu;Shuhan Bai;Jian Zhou;Fei Wu","doi":"10.1109/TCAD.2025.3602747","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3602747","url":null,"abstract":"Mobile devices adopt DRAM-less solid-state storage drives (SSDs) as the flash storage to reduce power consumption and manufacturing costs, yet DRAM-less SSDs are significantly impacted by file fragmentation, thereby degrading the responsiveness of mobile devices. Existing methods to mitigate file fragmentation, including preallocation and defragmentation, face critical limitations. Preallocation prevents file fragmentation by reserving contiguous free logical block address (LBA) space for individual files. However, in the limited LBA space exposed by the SSD, contiguous free space is gradually consumed and fragmented by scattered data blocks, reducing the effectiveness of preallocation. Defragmentation recovers file access performance by reorganizing fragmented file layouts into contiguous ones. However, when applied to DRAM-less SSDs, defragmentation introduces excessive cache eviction of dirty mapping entries to the slow N<sc>and flash, causing significant performance disruption. This article presents Fraggle, a host-device co-design that mitigates file fragmentation on DRAM-less SSDs by preserving the efficacy of preallocation within an extended LBA space. To effectively manage the extended LBA space, Fraggle introduces two key components: 1) HashFTL, a compact, cache-efficient flash translation layer (FTL) mapping mechanism specifically optimized for DRAM-less SSDs and 2) a device-assisted space allocator that simultaneously reduces space allocation overhead and resolves layout imbalance issues in HashFTL caused by sparse LBA distribution. Evaluation results demonstrate that, compared to F2FS and state-of-the-art preallocation methods, Fraggle accelerates execution time by up to <inline-formula> <tex-math>$9.26times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$8.07times $ </tex-math></inline-formula> under SQLite and real-world mobile application workloads.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1262-1275"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Discovering Optimal Constant Matrix Multiplication Circuits With Boolean Satisfiability 发现具有布尔可满足性的最优常矩阵乘法电路

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-19 DOI: 10.1109/TCAD.2025.3612335

Nicolai Fiege;Peter Zipf

{"title":"Discovering Optimal Constant Matrix Multiplication Circuits With Boolean Satisfiability","authors":"Nicolai Fiege;Peter Zipf","doi":"10.1109/TCAD.2025.3612335","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3612335","url":null,"abstract":"When designing arithmetic circuits, the multiplication of a variable by a constant number can be performed by a series of add/subtract, and shift operations instead of a multiplication (e.g., <inline-formula> <tex-math>$7x = 2^{3}x {-} x = (x ll 3) - x)$ </tex-math></inline-formula>. This allows for significant reductions in complexity of multiplication circuits, as adders are typically much more hardware-efficient than a generic multiplier, and shift operations can be performed without any overhead by appropriately connecting the concerned signals. This concept extends to the multiplication of a constant matrix by a vector of variables, known as constant matrix multiplication (CMM). So far, there exists no way of discovering CMM algorithms with provably minimal add/subtract count. Here, we show how the CMM problem can be reduced to a series of Boolean satisfiability (SAT) problems, enabling the use of powerful SAT solvers to determine optimal solutions for arbitrary matrices. Modeling the problem in a closed mathematical framework allows us to straightforwardly extend our algorithm toward secondary objectives, namely word-size reductions of the add/subtract operations and pipelining for throughput maximization. Compared to state-of-the-art heuristic methods, we were consistently able to achieve improvements regarding the resulting implementation complexity, even for small but practical matrix sizes such as <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> or <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula>. These results enable a reduction in implementation costs for a wide range of practical applications such as digital filters, convolutional cores in artificial neural networks, or the multiplication by complex constants in discrete transforms like the fast Fourier transform.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2307-2320"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults 功能上可能的双周期门穷举故障的多周期测试

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-17 DOI: 10.1109/TCAD.2025.3611112

Irith Pomeranz

{"title":"Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults","authors":"Irith Pomeranz","doi":"10.1109/TCAD.2025.3611112","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3611112","url":null,"abstract":"Advanced delay fault models such as the two-cycle defect-aware, cell-aware, or gate-exhaustive fault models associate faults with pairs of input patterns of gates (or cells). The large numbers of faults defined for these fault models result in large test sets. This article addresses the need to control the size of a scan-based test set for two-cycle gate-exhaustive faults in two ways: 1) only functionally possible faults, i.e., faults that can cause a circuit to fail during functional operation, contribute new tests to the test set and 2) multicycle tests are used to increase the number of faults that each test can detect. The effectiveness of multicycle tests for advanced fault models results from the following key observation. Faults that are associated with the same gate cannot be detected by the same two-cycle test, but a multicycle test can detect several faults that are associated with the same gate by activating the faults at different clock cycles. The article describes a test compaction procedure that uses this observation and presents experimental results for benchmark circuits in an academic simulation environment to demonstrate its effectiveness.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2275-2279"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Securing Storage Instructions: A Hamming Weight Balancing Approach to Prevent Secret Leaks Through Side Channels 安全存储说明：一个汉明重量平衡方法，以防止秘密泄漏通过侧通道

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-24 DOI: 10.1109/TCAD.2025.3614099

Jianfeng Du;Zhu Wang;Aimin Yu

引用次数: 0

A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication 可靠稀疏矩阵乘法的故障感知体系结构

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-10-07 DOI: 10.1109/TCAD.2025.3618934

Yifan Song;Yuxuan Qiao;Changxu Liu;Yifei Feng;Junjie Zuo;Baoyu Fan;Fan Yang

{"title":"A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication","authors":"Yifan Song;Yuxuan Qiao;Changxu Liu;Yifei Feng;Junjie Zuo;Baoyu Fan;Fan Yang","doi":"10.1109/TCAD.2025.3618934","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3618934","url":null,"abstract":"With the advancement of artificial intelligence (AI), the reliability of AI accelerators has become increasingly critical. Moreover, sparse matrix multiplication has become a fundamental primitive of deep learning, which can enhance the efficiency of model training and inference. However, reduced redundancy in sparse pruning models increases their vulnerability to permanent faults. Thus, ensuring both efficiency and reliability in sparse matrix multiplication is critical. Most existing reliable AI accelerators are tailored for general matrix multiplication, leading to suboptimal efficiency when handling sparse matrix multiplication and incurring substantial hardware overhead to support fault tolerance. To address this, we propose a hardware–software co-design fault-aware architecture for reliable sparse matrix multiplication, with negligible additional area overhead. Specifically, based on the unstructured-pruned matrix, we propose fault-aware reordering for a sparse matrix at the algorithmic level, which mitigates faults through fine-grained data scheduling and further enables parallel computation by employing a sparsity-aware merging strategy. At the hardware level, we design a fault-tolerant sparse matrix accelerator based on an optimized systolic array for sparse matrices, incorporating bypass paths for faulty PEs. Experimental results demonstrate that our architecture can tolerate a fault rate of up to <inline-formula> <tex-math>$boldsymbol {10%}$ </tex-math></inline-formula>, achieving a recovery efficiency improvement of <inline-formula> <tex-math>$boldsymbol {1.89times !!! sim !! 7.11 times }$ </tex-math></inline-formula> compared to existing methods, with minimal area overhead.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2395-2408"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Photonic Interconnect Enabling Cross-Layer Scheduling for Chiplet-Based DNN Accelerators 基于芯片的DNN加速器的光子互连跨层调度

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-07-28 DOI: 10.1109/TCAD.2025.3593438

Yubo Zhang;Yaoyao Ye

{"title":"A Photonic Interconnect Enabling Cross-Layer Scheduling for Chiplet-Based DNN Accelerators","authors":"Yubo Zhang;Yaoyao Ye","doi":"10.1109/TCAD.2025.3593438","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3593438","url":null,"abstract":"deep neural networks (DNNs) demand high-performance and energy-efficient hardware acceleration. Chiplet-based DNN accelerators offer a promising solution for scaling up DNN acceleration by integrating multiple chiplets. However, efficient interconnection of these chiplets remains a significant challenge. Traditional metallic interconnect suffers from limitations in both bandwidth and energy efficiency. Photonic interconnect, offering ultrahigh bandwidth and energy efficiency, is emerging as a new interconnection technology for chiplet-based DNN accelerators. However, existing photonic interconnect designs lack the flexibility to implement advanced cross-layer scheduling, a crucial approach for enhancing computational efficiency in contemporary chiplet-based accelerators. To address this issue, we propose PICS, an efficient <underline>Photonic <underline>Interconnect design enabling flexible <underline>Cross-layer <underline>Scheduling for chiplet-based DNN accelerators. PICS incorporates a novel photonic interconnect architecture that facilitates efficient data transmission and flexible scheduling alongside a customized fine-grained scheduling and mapping framework. Compared to the state-of-the-art accelerator employing exclusively metallic interconnects with the state-of-the-art cross-layer scheduling framework, PICS demonstrates an average reduction of 9.5% and 31.9% in latency and energy consumption. Compared to the state-of-the-art accelerator employing photonic interconnects with the layer-sequential scheduling framework, PICS achieves an average reduction of 47.2% and 26.0% in latency and energy consumption.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2123-2135"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MiniBuf: An On-Chip Buffer Allocation Framework Toward Minimizing Buffer Size and Latency for Memristor-Based CNN Accelerator MiniBuf：一个片上缓冲区分配框架，用于最小化基于忆阻器的CNN加速器的缓冲区大小和延迟

IF 3.6 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-08-19 DOI: 10.1109/TCAD.2025.3600366

Ruihua Yu;Chenhuan Zou;Jiaming Li;Bin Gao;Jianshi Tang;He Qian;Huaqiang Wu

{"title":"MiniBuf: An On-Chip Buffer Allocation Framework Toward Minimizing Buffer Size and Latency for Memristor-Based CNN Accelerator","authors":"Ruihua Yu;Chenhuan Zou;Jiaming Li;Bin Gao;Jianshi Tang;He Qian;Huaqiang Wu","doi":"10.1109/TCAD.2025.3600366","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3600366","url":null,"abstract":"Memristor-based convolutional neural network (CNN) accelerators have gained considerable attention due to their low latency and high energy efficiency, making them promising candidates for edge acceleration. Alongside statically stored model weights, dynamically generated intermediate feature maps during inference occupy a significant portion of the on-chip buffer capacity and directly affect the efficiency of hardware pipeline execution. However, there is a lack of theoretical analysis and methods for efficiently allocating on-chip buffer for feature map data. To address this gap, this article implements three innovative aspects. First, a mathematical model is developed to estimate the minimal buffer size required for pipelined inference of CNNs on memristor-based accelerators, offering accurate and swift evaluations of the buffer size requirement. Second, based on this model, the article establishes mathematical conditions for buffer requirements to maintain a blocking-free pipeline during CNN inference, providing theoretical guidance for on-chip buffer allocation strategies. Third, a simulation-in-loop optimization method is proposed to further reduce latency by efficiently increasing the buffer size of critical layers. To validate our proposed model and method, evaluations were conducted on five representative models: ResNet-18, ResNet-50, YOLO-v5, U-Net, and Faster-RCNN-FPN. The results reveal a remarkably low average estimation error of only 2.6% between the mathematical model and the experimentally measured results, with the maximum error still below 10%. Moreover, our simulation-in-loop optimization strategy achieved significant latency reductions ranging from 5.3% to 57.5% across the five models.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1146-1159"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0