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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

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LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection LithoHoD：由光刻模拟器驱动的集成电路布局热点检测框架
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-18 DOI: 10.1109/tcad.2024.3463539
Hao-Chiang Shao, Guan-Yu Chen, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
{"title":"LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection","authors":"Hao-Chiang Shao, Guan-Yu Chen, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu","doi":"10.1109/tcad.2024.3463539","DOIUrl":"https://doi.org/10.1109/tcad.2024.3463539","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"2 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142258216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits 绝热量子通量-参数电子电路的缓冲器和分流器插入技术
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-18 DOI: 10.1109/tcad.2024.3461573
Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho
{"title":"Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits","authors":"Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho","doi":"10.1109/tcad.2024.3461573","DOIUrl":"https://doi.org/10.1109/tcad.2024.3461573","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"29 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142258218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sobol Sequence Optimization for Hardware-Efficient Vector Symbolic Architectures 针对硬件高效矢量符号架构的 Sobol 序列优化
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-18 DOI: 10.1109/tcad.2024.3463544
Sercan Aygun, M. Hassan Najafi
{"title":"Sobol Sequence Optimization for Hardware-Efficient Vector Symbolic Architectures","authors":"Sercan Aygun, M. Hassan Najafi","doi":"10.1109/tcad.2024.3463544","DOIUrl":"https://doi.org/10.1109/tcad.2024.3463544","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"10 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142269388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers ATOM： 运算放大器拓扑自动合成框架
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-18 DOI: 10.1109/tcad.2024.3463534
Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, Xuan Zeng
{"title":"ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers","authors":"Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, Xuan Zeng","doi":"10.1109/tcad.2024.3463534","DOIUrl":"https://doi.org/10.1109/tcad.2024.3463534","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"1 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142258253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation 带频率补偿的模拟集成电路自动拓扑合成
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-18 DOI: 10.1109/tcad.2024.3462904
Zhenxin Zhao, Jun Liu, Wensheng Zhao, Lihong Zhang
{"title":"Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation","authors":"Zhenxin Zhao, Jun Liu, Wensheng Zhao, Lihong Zhang","doi":"10.1109/tcad.2024.3462904","DOIUrl":"https://doi.org/10.1109/tcad.2024.3462904","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"117 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142258217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mitigating The Impact of ReRAM I-V Nonlinearity and IR Drop via Fast Offline Network Training 通过快速离线网络训练减轻 ReRAM I-V 非线性和 IR 下降的影响
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-13 DOI: 10.1109/tcad.2024.3459855
Sugil Lee, Mohammed E. Fouda, Chenghao Quan, Jongeun Lee, Ahmed Eltawil, Fadi Kurdahi
{"title":"Mitigating The Impact of ReRAM I-V Nonlinearity and IR Drop via Fast Offline Network Training","authors":"Sugil Lee, Mohammed E. Fouda, Chenghao Quan, Jongeun Lee, Ahmed Eltawil, Fadi Kurdahi","doi":"10.1109/tcad.2024.3459855","DOIUrl":"https://doi.org/10.1109/tcad.2024.3459855","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"206 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142257890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Low Power BIST for Automotive SoC With Periodic Pattern Type Selection 一种用于汽车系统级芯片的高效低功耗 BIST，具有周期性图案类型选择功能
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-11 DOI: 10.1109/tcad.2024.3457795
Jongho Park, Sangjun Lee, Hyemin Kim, Jaeyoung Joung, Jaehyun Kim, Sungho Kang
{"title":"An Efficient Low Power BIST for Automotive SoC With Periodic Pattern Type Selection","authors":"Jongho Park, Sangjun Lee, Hyemin Kim, Jaeyoung Joung, Jaehyun Kim, Sungho Kang","doi":"10.1109/tcad.2024.3457795","DOIUrl":"https://doi.org/10.1109/tcad.2024.3457795","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"131 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142176748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Utilization of Multi-Skewed Multi-Bit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach 设计和利用多倾斜多比特触发器单元实现时序优化：设计与技术协同优化方法
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-11 DOI: 10.1109/tcad.2024.3457834
Suwan Kim, Taewhan Kim
{"title":"Design and Utilization of Multi-Skewed Multi-Bit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach","authors":"Suwan Kim, Taewhan Kim","doi":"10.1109/tcad.2024.3457834","DOIUrl":"https://doi.org/10.1109/tcad.2024.3457834","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"27 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142176749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Contract-Based Hierarchical Modeling and Traceability of Heterogeneous Requirements 基于合同的分层建模和异构需求的可追溯性
IF 2.7 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-10 DOI: 10.1109/TCAD.2024.3447213
Nikhil Vijay Naik;Alessandro Pinto;Pierluigi Nuzzo
{"title":"Contract-Based Hierarchical Modeling and Traceability of Heterogeneous Requirements","authors":"Nikhil Vijay Naik;Alessandro Pinto;Pierluigi Nuzzo","doi":"10.1109/TCAD.2024.3447213","DOIUrl":"10.1109/TCAD.2024.3447213","url":null,"abstract":"The design of complex mission-critical systems often follows a layered approach, which may lead to complicated, multilevel, multiviewpoint requirement hierarchies. This heterogeneity makes it challenging to guarantee the traceability of the requirements across levels of abstraction and, consequently, the satisfaction of the requirements by a system implementation, especially when requirements at different abstraction levels are expressed using different mathematical formalisms and modeling languages. In this article, we address this challenge by introducing heterogeneous hierarchical contract networks (HHCNs), a formal model based on a graph of assume-guarantee contracts, for capturing and analyzing heterogeneous requirement hierarchies. We formulate the requirement traceability validation problem in terms of contract refinement relations between nodes in an HHCN. We then define contract embeddings to enable reasoning about refinements across levels of abstraction in the HHCN that are expressed using heterogeneous formalisms. Contract embeddings leverage the notion of conservative approximation to rigorously map contracts across levels of abstraction while ensuring that refinement is preserved independently of the formalism to which the contracts are mapped. We illustrate their effectiveness on a case study motivated by a multiagent autonomous lunar rover mission.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"43 11","pages":"4298-4309"},"PeriodicalIF":2.7,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142176753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning 先验增强型 GRL：通过图形表示学习探索微架构设计空间
IF 2.9 3区 计算机科学
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-10 DOI: 10.1109/tcad.2024.3457376
Zheng Wu, Jinyi Shen, Xiaoling Yi, Li Shang, Fan Yang, Xuan Zeng
{"title":"Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning","authors":"Zheng Wu, Jinyi Shen, Xiaoling Yi, Li Shang, Fan Yang, Xuan Zeng","doi":"10.1109/tcad.2024.3457376","DOIUrl":"https://doi.org/10.1109/tcad.2024.3457376","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"1 1","pages":""},"PeriodicalIF":2.9,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142176751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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