IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献_第10页

ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators 硅光子微环谐振器工艺变化弹性设计的自动化设计与分析框架

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-22 DOI: 10.1109/TCAD.2024.3505078

Asif Mirza;Ryan E. Gloekler;Sudeep Pasricha;Mahdi Nikdast

{"title":"ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators","authors":"Asif Mirza;Ryan E. Gloekler;Sudeep Pasricha;Mahdi Nikdast","doi":"10.1109/TCAD.2024.3505078","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3505078","url":null,"abstract":"Silicon photonics promises revolutionary advancements in communication and computing, leveraging the integration of photonic components onto silicon platforms. However, a critical challenge remains in achieving robust device performance under inevitable process variations inherent in CMOS fabrication. Existing design methodologies often fall short in assessing and mitigating the impact of these variations on device behavior, particularly in microring resonators (MRRs). To address this challenge, we present a novel, comprehensive workflow for designing process-variation-resilient silicon photonic MRRs, which we have integrated into a variation-aware design optimization framework called process variation analysis tool. Our approach seamlessly integrates process-variation robustness directly into the design phase, enabling early optimization of device performance characteristics. By exploring diverse process-variation scenarios, our workflow provides crucial insights into design tradeoffs and strategies for enhancing MRR robustness. Furthermore, we achieve this analysis efficiently through the use of compact models, striking a balance between accuracy and computational cost. This approach significantly reduces design cycles and resource requirements, offering a practical and cost-effective path toward optimizing MRR performance under real-world manufacturing conditions.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1788-1792"},"PeriodicalIF":2.7,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits 逻辑芯片和内存芯片的玻璃贴片集成：PPA 和电源/信号完整性优势

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-21 DOI: 10.1109/TCAD.2024.3504361

Pruek Vanna-Iampikul;Seungmin Woo;Serhat Erdogan;Lingjun Zhu;Mohanalingam Kathaperumal;Ravi Agarwal;Ram Gupta;Kevin Rinebold;Madhavan Swaminathan;Sung Kyu Lim

{"title":"Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits","authors":"Pruek Vanna-Iampikul;Seungmin Woo;Serhat Erdogan;Lingjun Zhu;Mohanalingam Kathaperumal;Ravi Agarwal;Ram Gupta;Kevin Rinebold;Madhavan Swaminathan;Sung Kyu Lim","doi":"10.1109/TCAD.2024.3504361","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3504361","url":null,"abstract":"Glass interposers have become a compelling option for 2.5-D heterogeneous integration compared to silicon. It allows 3-D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top at low cost. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this study, we investigate the power, performance, area (PPA), signal integrity (SI) and power integrity (PI) advantages of 3-D stacking afforded by glass interposers over silicon interposers. Our research employs a chiplet/package co-design approach, progressing from an register-transfer-level description of RISC-V chiplets to final graphic data system (GDS) layouts, utilizing TSMC 28 nm for chiplets and Georgia Tech’s 3-D glass packaging for the interposer. Compared to silicon, glass interposers offer a <inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula> reduction in area, a <inline-formula> <tex-math>$21times $ </tex-math></inline-formula> reduction in wire length, a 17.72% reduction in full-chip power consumption, a 64.7% increase in SI and a <inline-formula> <tex-math>$10times $ </tex-math></inline-formula> improvement in PI, with a 35% increase in thermal. Furthermore, we provide a detailed comparative analysis with 3-D Silicon technologies. It not only highlights the competitive advantages of glass interposers, but also provides critical insights into each design’s potential limitations and optimization opportunities.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1954-1967"},"PeriodicalIF":2.7,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information 电气和电子工程师学会《集成电路与系统计算机辅助设计》（IEEE Transactions on Computer-Aided Design of Integrated Circits and Systems）出版物信息

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-21 DOI: 10.1109/TCAD.2024.3498115

引用次数: 0

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information 电气和电子工程师学会《集成电路和系统计算机辅助设计期刊》（IEEE Transactions on Computer-Aided Design of Integrated Circits and Systems）社会信息

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-21 DOI: 10.1109/TCAD.2024.3498113

引用次数: 0

Effective and Efficient Parallel Qubit Mapper 有效和高效的并行量子比特映射器

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-18 DOI: 10.1109/TCAD.2024.3500784

Hao Fu;Mingzheng Zhu;Fangzheng Chen;Chi Zhang;Jun Wu;Wei Xie;Xiang-Yang Li

{"title":"Effective and Efficient Parallel Qubit Mapper","authors":"Hao Fu;Mingzheng Zhu;Fangzheng Chen;Chi Zhang;Jun Wu;Wei Xie;Xiang-Yang Li","doi":"10.1109/TCAD.2024.3500784","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3500784","url":null,"abstract":"Quantum computing has been accumulating tremendous attention in recent years. In current superconducting quantum processors, each qubit can only be connected with a limited number of neighbors. Therefore, the original quantum circuit should be converted to a hardware-dependent circuit, and this process is called qubit mapping and routing, in which typically extra SWAP gates need to be inserted. Due to a limited qubit lifetime, one of the main objectives of qubit mapping and routing is to minimize the circuit depth, which is a time-consuming process. By studying several existing greedy mappers, we extract and analyze two patterns that significantly impact the mapping and routing performance. Then, we propose a sliding window method named SWin, which dramatically reduces the computational cost with negligible performance degradation. For devices with constrained executable circuit depth, we propose SWin+, which introduces adaptive circuit slicing methods with VF<inline-formula> <tex-math>$2+ {+}$ </tex-math></inline-formula> subgraph isomorphism initial mapping methods. Compared with the state-of-the-art greedy methods, SWin can find an effective result by up to 39% depth decrease, on average of 16% for large-scale circuits. Moreover, SWin can be easily modified to be noise-aware, while the depth reduction will yield better performance for real execution. Furthermore, SWin still performs well for various chip couplings. SWin+ significantly enhances processing efficiency, achieving improvements up to <inline-formula> <tex-math>$22.3times $ </tex-math></inline-formula>, with an average increase of <inline-formula> <tex-math>$6.1times $ </tex-math></inline-formula>. Concurrently, it maintains the effectiveness of the transformed circuit depth.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1774-1787"},"PeriodicalIF":2.7,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Delay-Driven Rectilinear Steiner Tree Construction 延迟驱动的直角斯坦纳树构造

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-18 DOI: 10.1109/TCAD.2024.3501932

Hongxi Wu;Xingquan Li;Liang Chen;Bei Yu;Wenxing Zhu

{"title":"Delay-Driven Rectilinear Steiner Tree Construction","authors":"Hongxi Wu;Xingquan Li;Liang Chen;Bei Yu;Wenxing Zhu","doi":"10.1109/TCAD.2024.3501932","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3501932","url":null,"abstract":"Timing-driven routing is crucial in complex circuit design. Existing shallow-light Steiner tree construction methods balance between wire length (WL) and source-sink path length (PL) but lack in delay. Conversely, previous delay-driven methods prioritize delay but result in longer WL and PL, making them suboptimal. In this article, we show that simultaneously reducing the WL and PL can effectively reduce the delay. Furthermore, we investigate how delay changes during the reduction of PL. Guided by the theoretical findings, we develop a rectilinear shallow-light Steiner tree construction algorithm designed to reduce delay meanwhile maintaining a bounded WL. Furthermore, a delay-driven edge shifting algorithm is proposed to fine tune the tree’s topology, further reducing delay. We show that our proposed edge shifting algorithm can return a local Pareto optimal solution when repeatedly applied. Experimental results show that our algorithm achieves the lowest total delay compared to previous methods while maintaining competitive WL. Moreover, for nets with pins that have timing information, our algorithm can generate the most suitable Steiner Tree based on the timing information. In addition, extended experiments highlight the positive impact of constructing rectilinear Steiner trees with minimized total delay. Our codes will be available at <uri>https://github.com/Whx97/Delay-driven-Steiner-Tree</uri>.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1928-1941"},"PeriodicalIF":2.7,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine RuleLearner：从反向光刻技术引擎中提取 OPC 规则

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-15 DOI: 10.1109/TCAD.2024.3499909

Ziyang Yu;Su Zheng;Wenqian Zhao;Shuo Yin;Xiaoxiao Liang;Guojin Chen;Yuzhe Ma;Bei Yu;Martin D. F. Wong

{"title":"RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine","authors":"Ziyang Yu;Su Zheng;Wenqian Zhao;Shuo Yin;Xiaoxiao Liang;Guojin Chen;Yuzhe Ma;Bei Yu;Martin D. F. Wong","doi":"10.1109/TCAD.2024.3499909","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3499909","url":null,"abstract":"Model-based optical proximity correction (OPC) with subresolution assist feature (SRAF) generation is a critical standard practice for compensating lithography distortions in the fabrication of integrated circuits at advanced technology nodes. Typical model-based OPC and SRAF algorithms involve the selection of user-controlled rule parameters. Conventionally, these rules are heuristically determined and applied globally throughout the correction regions, which can be time consuming and require expert knowledge of the tool. Additionally, the correlations of rule parameters to the objectives are highly nonlinear. All these factors make designing a high-performance OPC engine for complex metal designs a nontrivial task. This article proposes RuleLearner, a comprehensive mask optimization system designed for SRAF generation and model-based OPC in real industrial scenarios. The proposed framework learns from the guidance of an information-augmented inverse lithography technique engine, which, although expressive for complex designs, is expensive to generate refined masks for a whole set of design clips. Considering the nonlinearity and the tradeoff between local and global performance, the extracted rule value distributions are further optimized with customized natural gradients. The sophisticated SRAF generation, the edge segmentation and movements are then guided by the rule parameter. Experimental results show that RuleLearner can be applied across different complex design patterns and achieve the best lithographic performance and computational efficiency.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1915-1927"},"PeriodicalIF":2.7,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Direct Search Procedure for Functional Compaction With Improved Fault Coverage 改进故障覆盖率的功能压缩直接搜索程序

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-14 DOI: 10.1109/TCAD.2024.3499898

Irith Pomeranz

{"title":"Direct Search Procedure for Functional Compaction With Improved Fault Coverage","authors":"Irith Pomeranz","doi":"10.1109/TCAD.2024.3499898","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3499898","url":null,"abstract":"An important component of ensuring system reliability is the application of functional tests. Functional test sequences are available after simulation-based design verification, they can be extracted from application programs, or generated for target faults. Functional test sequences can be long, and test compaction at the gate-level is important for reducing the test application time without losing fault coverage. Experimental results with several test compaction procedures indicate that test compaction sometimes leads accidentally to an increased fault coverage. Such an increase was observed recently with a gate-level test compaction procedure that has the unique property of restoring functional operation conditions after parts of a sequence are eliminated. The contribution of this article is to use this property of the test compaction procedure to increase the fault coverage directly, in a targeted manner, while compacting the sequence. Experimental results for benchmark circuits in an academic environment demonstrate a significant fault coverage increase combined with significant test compaction.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1981-1990"},"PeriodicalIF":2.7,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM 一种基于最大故障采集和快速分析的HBM内置自修复方法

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-14 DOI: 10.1109/TCAD.2024.3499903

Joonsik Yoon;Hayoung Lee;Youngki Moon;Seung Ho Shin;Sungho Kang

{"title":"A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM","authors":"Joonsik Yoon;Hayoung Lee;Youngki Moon;Seung Ho Shin;Sungho Kang","doi":"10.1109/TCAD.2024.3499903","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3499903","url":null,"abstract":"High bandwidth memory (HBM) represents a significant advancement in memory technology, requiring quick and accurate data processing. Built-in self-repair (BISR) is crucial for ensuring high-capacity and reliable memories, as it automatically detects and repairs faults within memory systems, preventing data loss and enhancing overall memory reliability. The proposed BISR aims to enhance the repair rate and reliability by using a content-addressable memory structure that operates effectively in both offline and online modes. Furthermore, a new redundancy analysis algorithm reduces both analysis time and area overhead by converting fault information into a matrix format and focusing on fault-free areas for each repair solution. Experimental results demonstrate that the proposed BISR improves repair rates and derives a final repair solution immediately after the test sequences are completed. Moreover, hardware comparisons have shown that the proposed approach reduces the area overhead as memory size increases. Consequently, the proposed BISR enhances the overall performance of BISR and the reliability of HBM.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"2014-2025"},"PeriodicalIF":2.7,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set COCO：基于配置的压缩测试集的压缩

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-14 DOI: 10.1109/TCAD.2024.3499907

Irith Pomeranz

{"title":"COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set","authors":"Irith Pomeranz","doi":"10.1109/TCAD.2024.3499907","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3499907","url":null,"abstract":"Comprehensive defect coverage requires test sets that detect faults from several fault models. A test set is typically topped-off to detect faults from an additional fault model that are not already detected. This creates large test sets whose last tests detect small numbers of additional faults. Reducing the storage requirements of topped-off test sets (or test sets for fault models with large numbers of faults) is the topic of this article. Instead of storing the last tests in their entirety, it was shown previously that it is possible to produce the last tests of the test set from tests that appear earlier by complementing single bits. The storage requirements are reduced when only complemented bits are stored; however, the number of applied tests is increased. This article observes that changing the configuration by which decompressed test data are shifted into scan chains produces new tests that are effective in replacing tests at the end of a topped-off test set without increasing the number of applied tests. This approach is developed in this article in an academic environment and implemented using academic software tools. It is applied to benchmark circuits to demonstrate its effectiveness.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1991-1999"},"PeriodicalIF":2.7,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0