B-HTRecognizer:使用图注意网络的位硬件木马定位

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Han Zhang;Zhenyu Fan;Yinhao Zhou;Ying Li
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引用次数: 0

摘要

硬件木马(ht)是由不受信任的供应商注入集成电路(IC)的恶意修改,由于其高度破坏性的性质,对电路设计构成了重大威胁。高温超导的隐蔽特性给检测方法带来了挑战,例如需要可转移的未知电路检测,涉及大量的人工工作,以及难以进行细粒度定位。为了解决这些问题,我们提出了B-HTRecognizer,这是一种新的基于学习的分类方法,它利用HT相似性在位水平上自动定位未知设计中的HT。在本研究中,我们使用图注意网络(GAT)将Verilog硬件描述语言(HDL)设计转换为位级边缘特征数据流图(DFGs),用于HTs的多维特征提取。位级特征提取在处理触发隐藏ht时可以获得更好的性能,这很可能绕过现有的GNN解决方案。此外,我们构建了一个名为trustthub IMEex的开源HT数据集,该数据集可以在https://www.scidb.cn/en/anonymous/QjNFdmUy上公开获取,该数据集扩展了trustthub数据集,以方便有效的训练和精确的定位。通过不同设计的严格实验,我们提出的方法在非交叉设计设置下达到84%的准确率和93%的召回率,在32位RISC-V设计的交叉设计测试中召回率达到77%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
B-HTRecognizer: Bitwise Hardware Trojan Localization Using Graph Attention Networks
Hardware Trojans (HTs), which are malicious modifications injected into an integrated circuit (IC) by untrusted vendors, pose a significant threat to circuit design due to their highly destructive nature. The covert characteristics of HTs present challenges for detection methods, such as the requirement for transferable unknown circuit detection, the extensive manual effort involved, and the difficulty in fine-grained localization. To address these issues, we present B-HTRecognizer, a novel learning-based classification methodology that leverages HT similarities to automatically localize HTs in unknown designs at the bit level. In this study, we convert Verilog hardware description language (HDL) design into bit-level edge-featured data flow graphs (DFGs) using graph attention network (GAT) for multidimensional feature extraction of HTs. The bit-level feature extraction can achieve better performance when dealing with Trigger-hidden HTs, which are highly likely to bypass existing GNN solutions. Furthermore, we construct an open-source HT dataset named TrustHub IMEex The HTs dataset is publicly available at https://www.scidb.cn/en/anonymous/QjNFdmUy which extends the TrustHub dataset to facilitate effective training and precise localization. Through rigorous experimentation across different designs, our proposed method achieves 84% precision and 93% recall in noncross-design settings, and a recall rate of 77% on a 32-bit RISC-V design in cross-design testing.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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