{"title":"B-HTRecognizer:使用图注意网络的位硬件木马定位","authors":"Han Zhang;Zhenyu Fan;Yinhao Zhou;Ying Li","doi":"10.1109/TCAD.2024.3518417","DOIUrl":null,"url":null,"abstract":"Hardware Trojans (HTs), which are malicious modifications injected into an integrated circuit (IC) by untrusted vendors, pose a significant threat to circuit design due to their highly destructive nature. The covert characteristics of HTs present challenges for detection methods, such as the requirement for transferable unknown circuit detection, the extensive manual effort involved, and the difficulty in fine-grained localization. To address these issues, we present B-HTRecognizer, a novel learning-based classification methodology that leverages HT similarities to automatically localize HTs in unknown designs at the bit level. In this study, we convert Verilog hardware description language (HDL) design into bit-level edge-featured data flow graphs (DFGs) using graph attention network (GAT) for multidimensional feature extraction of HTs. The bit-level feature extraction can achieve better performance when dealing with Trigger-hidden HTs, which are highly likely to bypass existing GNN solutions. Furthermore, we construct an open-source HT dataset named TrustHub IMEex The HTs dataset is publicly available at <uri>https://www.scidb.cn/en/anonymous/QjNFdmUy</uri> which extends the TrustHub dataset to facilitate effective training and precise localization. Through rigorous experimentation across different designs, our proposed method achieves 84% precision and 93% recall in noncross-design settings, and a recall rate of 77% on a 32-bit RISC-V design in cross-design testing.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2240-2252"},"PeriodicalIF":2.9000,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"B-HTRecognizer: Bitwise Hardware Trojan Localization Using Graph Attention Networks\",\"authors\":\"Han Zhang;Zhenyu Fan;Yinhao Zhou;Ying Li\",\"doi\":\"10.1109/TCAD.2024.3518417\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Hardware Trojans (HTs), which are malicious modifications injected into an integrated circuit (IC) by untrusted vendors, pose a significant threat to circuit design due to their highly destructive nature. The covert characteristics of HTs present challenges for detection methods, such as the requirement for transferable unknown circuit detection, the extensive manual effort involved, and the difficulty in fine-grained localization. To address these issues, we present B-HTRecognizer, a novel learning-based classification methodology that leverages HT similarities to automatically localize HTs in unknown designs at the bit level. In this study, we convert Verilog hardware description language (HDL) design into bit-level edge-featured data flow graphs (DFGs) using graph attention network (GAT) for multidimensional feature extraction of HTs. The bit-level feature extraction can achieve better performance when dealing with Trigger-hidden HTs, which are highly likely to bypass existing GNN solutions. Furthermore, we construct an open-source HT dataset named TrustHub IMEex The HTs dataset is publicly available at <uri>https://www.scidb.cn/en/anonymous/QjNFdmUy</uri> which extends the TrustHub dataset to facilitate effective training and precise localization. Through rigorous experimentation across different designs, our proposed method achieves 84% precision and 93% recall in noncross-design settings, and a recall rate of 77% on a 32-bit RISC-V design in cross-design testing.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 6\",\"pages\":\"2240-2252\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2024-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10802937/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10802937/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
B-HTRecognizer: Bitwise Hardware Trojan Localization Using Graph Attention Networks
Hardware Trojans (HTs), which are malicious modifications injected into an integrated circuit (IC) by untrusted vendors, pose a significant threat to circuit design due to their highly destructive nature. The covert characteristics of HTs present challenges for detection methods, such as the requirement for transferable unknown circuit detection, the extensive manual effort involved, and the difficulty in fine-grained localization. To address these issues, we present B-HTRecognizer, a novel learning-based classification methodology that leverages HT similarities to automatically localize HTs in unknown designs at the bit level. In this study, we convert Verilog hardware description language (HDL) design into bit-level edge-featured data flow graphs (DFGs) using graph attention network (GAT) for multidimensional feature extraction of HTs. The bit-level feature extraction can achieve better performance when dealing with Trigger-hidden HTs, which are highly likely to bypass existing GNN solutions. Furthermore, we construct an open-source HT dataset named TrustHub IMEex The HTs dataset is publicly available at https://www.scidb.cn/en/anonymous/QjNFdmUy which extends the TrustHub dataset to facilitate effective training and precise localization. Through rigorous experimentation across different designs, our proposed method achieves 84% precision and 93% recall in noncross-design settings, and a recall rate of 77% on a 32-bit RISC-V design in cross-design testing.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.