FPGA Technology Mapping With Adaptive Gate Decomposition

Abstract

FPGA technology mapping is an extensively studied problem. There is functional decomposition as well as graph covering-based approaches. For efficiency consideration, most existing algorithms are graph covering-based. However, logic synthesis can affect the graph covering results significantly. In this article, we propose an FPGA mapping algorithm with gate decomposition. Bin-packing is used to generate gate decompositions during mapping to avoid the decomposition choice pregeneration problem in existing approaches. Our results show that our algorithm can get an average of 13% area reduction over the state-of-the-art lossless synthesis-based mapping algorithm in ABC. When compared with industrial tool Vivado, we can get a significant area reduction of 35% on average.