A Reduced State-Space Generation Method for Concurrent Systems Based on CPN-PR Model

IF 2.9 3区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-11 DOI:10.1109/TCAD.2024.3515857

Wenjie Zhong;Tao Sun;Jian-Tao Zhou;Zhuowei Wang;Xiaoyu Song

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引用次数: 0

Abstract

Colored Petri nets (CPNs) provide descriptions of the concurrent behaviors for software and hardware. Model checking based on CPNs is an effective method to simulate and verify the concurrent behavior in system design. However, the model-checking method traverses the full state space, which suffers from the state-space explosion problem. A reduced state-space generation method related to the property of concurrent systems is proposed. Specifically, we extend CPNs to define a property-related model (CPN-PR) and give a property-related analysis method whose results can be used to generate the CPN-PR model. A reduced state-space generation method is developed based on enabled binding element filtering rules. The stutter trace equivalence between the state spaces of CPN and CPN-PR has been proven by showing that the reduced state space may not change the model-checking result. A comparison experiment is conducted to demonstrate the effectiveness of our method.

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基于CPN-PR模型的并行系统简化状态空间生成方法

彩色Petri网（cpn）描述了软件和硬件的并发行为。基于cpn的模型检验是仿真和验证系统设计中并发行为的有效方法。然而，模型检查方法遍历整个状态空间，存在状态空间爆炸问题。针对并发系统的特性，提出了一种简化的状态空间生成方法。具体而言，我们将cpn扩展为属性相关模型（CPN-PR），并给出了一种属性相关分析方法，其结果可用于生成CPN-PR模型。基于启用的绑定元素过滤规则，开发了一种简化的状态空间生成方法。证明了CPN和CPN- pr状态空间之间的口吃轨迹等价性，证明了简化后的状态空间不会改变模型检查结果。通过对比实验验证了该方法的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 工程技术-工程：电子与电气

CiteScore

5.60

自引率

13.80%

发文量

500

审稿时长

7 months

期刊介绍： The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.