Madani Bachir;Azzaz Mohamed Salah;Sadoudi Said;Kaibou Redouane;Bruno da Silva
{"title":"Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs","authors":"Madani Bachir;Azzaz Mohamed Salah;Sadoudi Said;Kaibou Redouane;Bruno da Silva","doi":"10.1109/TCAD.2024.3518412","DOIUrl":null,"url":null,"abstract":"Modular addition is a fundamental operation in public-key cryptographic algorithms operating in finite fields, such as elliptic curve cryptography (ECC), Chebyshev polynomials, and post-quantum cryptography (PQC). The performance of these cryptographic algorithms is limited by the conventional modular adder approach, which incorporates two cascaded adders in series. This approach leads to a doubled critical path delay, ultimately causing a decrease in frequency despite utilizing a high-performance adder. This research presents a high-performance, low-area architecture for a modular adder, employing a novel approach. Specifically designed for various prime fields recommended in public key cryptography, the architecture optimally utilizes the carry chain and exploits the structural advantages of the 7-series field programmable gate array and series beyond. Implementation results demonstrate superior performance, achieving operating frequencies of 290.0 MHz for 192 bits and 205.5 MHz for 1024 bits. Notably, the proposed design performs modular addition in a single clock cycle, resulting in an approximate 57% frequency enhancement compared to the conventional approach. Consequently, this architecture stands as an optimal solution for systems demanding high-speed operations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2168-2180"},"PeriodicalIF":2.7000,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10802921/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Modular addition is a fundamental operation in public-key cryptographic algorithms operating in finite fields, such as elliptic curve cryptography (ECC), Chebyshev polynomials, and post-quantum cryptography (PQC). The performance of these cryptographic algorithms is limited by the conventional modular adder approach, which incorporates two cascaded adders in series. This approach leads to a doubled critical path delay, ultimately causing a decrease in frequency despite utilizing a high-performance adder. This research presents a high-performance, low-area architecture for a modular adder, employing a novel approach. Specifically designed for various prime fields recommended in public key cryptography, the architecture optimally utilizes the carry chain and exploits the structural advantages of the 7-series field programmable gate array and series beyond. Implementation results demonstrate superior performance, achieving operating frequencies of 290.0 MHz for 192 bits and 205.5 MHz for 1024 bits. Notably, the proposed design performs modular addition in a single clock cycle, resulting in an approximate 57% frequency enhancement compared to the conventional approach. Consequently, this architecture stands as an optimal solution for systems demanding high-speed operations.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.