Multistage Enhanced Diagnosis With Fault Candidate Reduction

Abstract

Logic diagnosis is essential for improving reliability and yield. In conventional diagnosis methods, although various methods are proposed to enhance the accuracy and resolution of logic diagnosis, there are still diagnosis results where the reported locations of defects are incorrect. Particularly in logic circuits, which contain a large number of gates, multiple faults can occur, not just single faults. Since the number of possible cases for multiple faults is significantly greater compared to single faults, the diagnosis of multiple faults is complicated. To address this problem, a new diagnosis method that uses a multistage process with fault candidate reduction is proposed. In the proposed method, machine learning is used with fault candidate reduction, and post-processing is performed after the use of machine learning. This proposed method allows for the analysis of multiple faults using only the test responses for single faults, demonstrating that this method can maintain sufficient accuracy and resolution for unexpected faults.