iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree

Abstract

The advancement of modern clock tree synthesis (CTS) encounters a bottleneck, primarily due to the difficulty in achieving multiobjective co-optimization among complex design processes. To concurrently optimize skew, latency, and load capacitance, we propose an iterative and hierarchical CTS framework, which is composed of clustering, topology generation and routing, buffering, and optimization. First, we introduce a capacitance-based metric to achieve adaptive balanced clustering and optimize the cluster results through simulated annealing. Second, to construct a clock tree with lower latency, load capacitance, and skew, we introduce the skew-latency-load tree (SLLT), which combines the advantages of bound skew tree and Steiner shallow-light tree, and we propose an effective SLLT construction algorithm. Third, to further optimize CTS result by buffering, we introduce the critical wirelength evaluation (CWE) to evaluate the capability of each buffer, and propose the insertion delay estimation (IDE) to reduce the evaluation bias during buffering, then design the iterative skew convergence algorithm (ISCA) to achieve complete convergence of skew. We validate our solution using 28 nm process technology. Compared to our method, the commercial tool increases skew, latency, and clock capacitance by 39.5%, 13.0%, and 18.5%, respectively, while the OpenROAD by 101.6%, 50.7%, and 25.5%, respectively.