On Optimizing Inter- and Intra-Chiplet Interconnection Topologies for Robust Multi-Chiplet Systems

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Xiaohang Wang;Miao Xu;Amit Kumar Singh;Yingtao Jiang;Mei Yang
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引用次数: 0

Abstract

Inter- and intra-chiplet interconnection networks play a vital role in the operation of many core systems made of multiple chiplets. However, these networks are susceptible to faults caused by manufacturing defects and attacks resulting from the malicious insertion of hardware Trojans and backdoors. Unlike conventional fault-tolerant or countermeasure methods, this article focuses on optimizing network robustness to withstand both faults and attacks, while considering the constraints of chiplet area and power budget. To achieve this, this article first defines network robustness as a quantifiable measure based on various network parameters, after which an optimization problem is formulated to optimize the robustness of the network topology. To efficiently solve this problem, a reinforcement learning algorithm is proposed. Experimental results demonstrate that the proposed method is capable of generating inter- and intra-chiplet interconnection networks that are significantly more robust than existing topology generation methods. Specifically, the proposed method improves robustness over ButterDonut and Kite, respectively, by an average of 10.88% and 14.06% under random faults and by 9.37% and 7.81% under targeted attacks. These experimental results confirm that the proposed method is capable of generating robust inter- and intra-chiplet interconnection networks that can withstand both faults and attacks. By optimizing the network topology’s robustness, it provides a valuable contribution to the design and security of chiplet-based core systems.
稳健性多晶片系统晶片间和晶片内互连拓扑优化研究
芯片间和芯片内互连网络在由多个芯片组成的核心系统的运行中起着至关重要的作用。但是,这些网络容易受到制造缺陷导致的故障和恶意插入硬件木马和后门的攻击。与传统的容错或对抗方法不同,本文在考虑芯片面积和功耗预算约束的同时,重点关注优化网络的鲁棒性,以抵御故障和攻击。为此,本文首先将网络鲁棒性定义为基于各种网络参数的可量化度量,然后制定优化问题来优化网络拓扑的鲁棒性。为了有效地解决这一问题,提出了一种强化学习算法。实验结果表明,该方法能够生成比现有拓扑生成方法具有更强鲁棒性的片间和片内互连网络。具体而言,该方法在ButterDonut和Kite的随机故障下,鲁棒性分别提高了10.88%和14.06%,在目标攻击下,鲁棒性分别提高了9.37%和7.81%。这些实验结果证实了该方法能够生成健壮的芯片间和芯片内互连网络,能够承受故障和攻击。通过优化网络拓扑的鲁棒性,为基于芯片的核心系统的设计和安全性提供了有价值的贡献。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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