Ruisi Zhang;Rachel Selina Rajarathnam;David Z. Pan;Farinaz Koushanfar
{"title":"集成电路物理设计知识产权保护的稳健水印框架","authors":"Ruisi Zhang;Rachel Selina Rajarathnam;David Z. Pan;Farinaz Koushanfar","doi":"10.1109/TCAD.2025.3552503","DOIUrl":null,"url":null,"abstract":"Physical design watermarking (WM) on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. This article presents <monospace>ICMarks</monospace>, a quality-preserving and robust WM framework for modern IC physical design. <monospace>ICMarks</monospace> embeds unique watermark signatures during the physical design’s placement stage, thereby authenticating the IC layout ownership. <monospace>ICMarks</monospace>’s novelty lies in 1) strategically identifying a region of cells to watermark with minimal impact on the layout performance and 2) a two-level WM framework for augmented robustness toward potential removal and forging attacks. Extensive evaluations on benchmarks of different design objectives and sizes validate that <monospace>ICMarks</monospace> incurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, we demonstrate <monospace>ICMarks</monospace> is robust against two major WM attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the WM schemes, the signatures cannot be removed without significantly undermining the layout quality.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3910-3923"},"PeriodicalIF":2.9000,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection\",\"authors\":\"Ruisi Zhang;Rachel Selina Rajarathnam;David Z. Pan;Farinaz Koushanfar\",\"doi\":\"10.1109/TCAD.2025.3552503\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Physical design watermarking (WM) on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. This article presents <monospace>ICMarks</monospace>, a quality-preserving and robust WM framework for modern IC physical design. <monospace>ICMarks</monospace> embeds unique watermark signatures during the physical design’s placement stage, thereby authenticating the IC layout ownership. <monospace>ICMarks</monospace>’s novelty lies in 1) strategically identifying a region of cells to watermark with minimal impact on the layout performance and 2) a two-level WM framework for augmented robustness toward potential removal and forging attacks. Extensive evaluations on benchmarks of different design objectives and sizes validate that <monospace>ICMarks</monospace> incurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, we demonstrate <monospace>ICMarks</monospace> is robust against two major WM attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the WM schemes, the signatures cannot be removed without significantly undermining the layout quality.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 10\",\"pages\":\"3910-3923\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2025-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10930928/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10930928/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection
Physical design watermarking (WM) on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. This article presents ICMarks, a quality-preserving and robust WM framework for modern IC physical design. ICMarks embeds unique watermark signatures during the physical design’s placement stage, thereby authenticating the IC layout ownership. ICMarks’s novelty lies in 1) strategically identifying a region of cells to watermark with minimal impact on the layout performance and 2) a two-level WM framework for augmented robustness toward potential removal and forging attacks. Extensive evaluations on benchmarks of different design objectives and sizes validate that ICMarks incurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, we demonstrate ICMarks is robust against two major WM attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the WM schemes, the signatures cannot be removed without significantly undermining the layout quality.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.