Yongshang Li;Yu Zhang;Haoning Deng;Mingyu Chen;Zhenyu Li
{"title":"近期量子模拟的连接感知合成和面向pauli的量子位映射","authors":"Yongshang Li;Yu Zhang;Haoning Deng;Mingyu Chen;Zhenyu Li","doi":"10.1109/TCAD.2024.3509794","DOIUrl":null,"url":null,"abstract":"Quantum simulation is the foundation for the design of many algorithms which share subroutines known as quantum simulation kernels. Optimizing the compilation of these kernels is crucial, involving two key components: 1) circuit synthesis and 2) qubit mapping. However, existing circuit synthesis methods either overlook qubit connectivity constraints (QCCs) or prioritize minimizing gate count over optimizing circuit depth. Similarly, current qubit mapping techniques do not work well with circuit synthesis methods. To address these limitations, we propose PauliForest, which comprises a connectivity-aware circuit synthesis algorithm and a Pauli-oriented qubit mapping algorithm. The synthesis algorithm employs heuristic strategies to generate shallower circuits, while the qubit mapping algorithm seamlessly collaborates with the circuit synthesis process. Compared to the state-of-the-art Paulihedral compiler, our approach significantly reduces both CNOT gate counts (by 13%) and circuit depths (by 25%). Experiments on a noisy simulator and a real superconducting quantum computer show that our algorithm can improve the fidelity of quantum circuit execution compared to Paulihedral.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2119-2129"},"PeriodicalIF":2.9000,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"PauliForest: Connectivity-Aware Synthesis and Pauli-Oriented Qubit Mapping for Near-Term Quantum Simulation\",\"authors\":\"Yongshang Li;Yu Zhang;Haoning Deng;Mingyu Chen;Zhenyu Li\",\"doi\":\"10.1109/TCAD.2024.3509794\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Quantum simulation is the foundation for the design of many algorithms which share subroutines known as quantum simulation kernels. Optimizing the compilation of these kernels is crucial, involving two key components: 1) circuit synthesis and 2) qubit mapping. However, existing circuit synthesis methods either overlook qubit connectivity constraints (QCCs) or prioritize minimizing gate count over optimizing circuit depth. Similarly, current qubit mapping techniques do not work well with circuit synthesis methods. To address these limitations, we propose PauliForest, which comprises a connectivity-aware circuit synthesis algorithm and a Pauli-oriented qubit mapping algorithm. The synthesis algorithm employs heuristic strategies to generate shallower circuits, while the qubit mapping algorithm seamlessly collaborates with the circuit synthesis process. Compared to the state-of-the-art Paulihedral compiler, our approach significantly reduces both CNOT gate counts (by 13%) and circuit depths (by 25%). Experiments on a noisy simulator and a real superconducting quantum computer show that our algorithm can improve the fidelity of quantum circuit execution compared to Paulihedral.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 6\",\"pages\":\"2119-2129\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2024-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10771974/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10771974/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
PauliForest: Connectivity-Aware Synthesis and Pauli-Oriented Qubit Mapping for Near-Term Quantum Simulation
Quantum simulation is the foundation for the design of many algorithms which share subroutines known as quantum simulation kernels. Optimizing the compilation of these kernels is crucial, involving two key components: 1) circuit synthesis and 2) qubit mapping. However, existing circuit synthesis methods either overlook qubit connectivity constraints (QCCs) or prioritize minimizing gate count over optimizing circuit depth. Similarly, current qubit mapping techniques do not work well with circuit synthesis methods. To address these limitations, we propose PauliForest, which comprises a connectivity-aware circuit synthesis algorithm and a Pauli-oriented qubit mapping algorithm. The synthesis algorithm employs heuristic strategies to generate shallower circuits, while the qubit mapping algorithm seamlessly collaborates with the circuit synthesis process. Compared to the state-of-the-art Paulihedral compiler, our approach significantly reduces both CNOT gate counts (by 13%) and circuit depths (by 25%). Experiments on a noisy simulator and a real superconducting quantum computer show that our algorithm can improve the fidelity of quantum circuit execution compared to Paulihedral.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.