发布求助
文献互助 智能选刊 最新文献

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.最新文献

筛选
英文 中文
Frequency tolerance of RF micromechanical disk resonators in polysilicon and nanocrystalline diamond structural materials 多晶硅和纳米晶金刚石结构材料中射频微机械圆盘谐振器的频率容限
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609329
Jing Wang, Yuan Xie, C. Nguyen
{"title":"Frequency tolerance of RF micromechanical disk resonators in polysilicon and nanocrystalline diamond structural materials","authors":"Jing Wang, Yuan Xie, C. Nguyen","doi":"10.1109/IEDM.2005.1609329","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609329","url":null,"abstract":"A statistical evaluation of the absolute and matching tolerances of the resonance frequencies of surface-micromachined micromechanical 1-port disk resonators is conducted by fabricating and measuring a large quantity (>100) of devices in both polysilicon and nanocrystalline diamond structural materials. Through this analysis, respective average resonance frequency absolute and matching tolerances of 450 ppm and 343 ppm for polysilicon, and 756 ppm and 392 ppm for diamond, have been demonstrated on a measured set of 6 dies on 4-inch wafers fabricated using university facilities. The measured matching tolerance is sufficient to allow implementation of RF pre-select or image-reject filters for wireless communications with a confidence interval better than 99.7% over tested dies without the need for frequency trimming","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"71 1","pages":"4 pp.-285"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89375355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS 用于高迁移率双通道CMOS的高k/金属栅极堆叠应变Si和Ge mosfet
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609288
Olivier Weber, Y. Bogumilowicz, Thomas Ernst, J. Hartmann, F. Ducroquet, F. Andrieu, Cecilia Dupre, L. Clavelier, C. L. Royer, Nikolay Cherkashin, Martin Hÿtch, D. Rouchon, H. Dansas, A. Papon, V. Carron, C. Tabone, S. Deleonibus
{"title":"Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS","authors":"Olivier Weber, Y. Bogumilowicz, Thomas Ernst, J. Hartmann, F. Ducroquet, F. Andrieu, Cecilia Dupre, L. Clavelier, C. L. Royer, Nikolay Cherkashin, Martin Hÿtch, D. Rouchon, H. Dansas, A. Papon, V. Carron, C. Tabone, S. Deleonibus","doi":"10.1109/IEDM.2005.1609288","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609288","url":null,"abstract":"Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the same process for a dual channel integration scheme. Compared to the HfO2/Si reference, X1.7 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET IDsat performance. This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics. For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO2 gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"42 1","pages":"137-140"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90573219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Experimental clarification of mobility determining factors in HfSiON CMISFET with various film compositions 实验澄清了不同薄膜组成的HfSiON CMISFET的迁移率决定因素
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609368
R. Iijima, M. Takayanagi, T. Yamaguchi, M. Koyama, A. Nishiyama
{"title":"Experimental clarification of mobility determining factors in HfSiON CMISFET with various film compositions","authors":"R. Iijima, M. Takayanagi, T. Yamaguchi, M. Koyama, A. Nishiyama","doi":"10.1109/IEDM.2005.1609368","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609368","url":null,"abstract":"Dominant scattering mechanisms for both electrons and holes in HfSiON MISFET were examined systematically by using the newly developed pulse measurement technique. Mobility determining factors for electrons and holes in various effective field (Eeff) regions were identified. In addition, the influence of two elements of Hf and N on the mobility in the operational Eeff region was investigated and guidelines for improving performance of HfSiON-CMOS devices were presented","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"232 1","pages":"421-424"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86692718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Program and SILC constraints on NC memories scaling: a monte carlo approach 程序和SILC对NC存储器缩放的限制:蒙特卡罗方法
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609542
R. Gusmeroli, A. Spinelli, C. Monzio Compagnoni, D. Ielmini, F. Morelli, A. Lacaita
{"title":"Program and SILC constraints on NC memories scaling: a monte carlo approach","authors":"R. Gusmeroli, A. Spinelli, C. Monzio Compagnoni, D. Ielmini, F. Morelli, A. Lacaita","doi":"10.1109/IEDM.2005.1609542","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609542","url":null,"abstract":"We performed 3D Monte Carlo simulations of SOI NAND nanocrystal memories investigating the scaling constraints due to both program failure and reliability concerns. We show that the NC density should be optimized as a trade-off between number fluctuation and SILC immunity and that proper optimization is needed in order to meet the 45 nm ITRS node requirements","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"18 1","pages":"1038-1041"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89972454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies 集成和优化嵌入sige，压缩和拉伸应力衬垫薄膜，并在先进的SOI CMOS技术的应力记忆
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609315
M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, T. Feudel, K. Frohberg, M. Gerhardt, A. Hellmich, K. Hempel, J. Hohage, P. Javorka, J. Klais, G. Koerner, M. Lenski, A. Neu, R. Otterbach, P. Press, C. Reichel, M. Trentsch, B. Trui, H. Salz, M. Schaller, H. Engelmann, O. Herzog, H. Ruelke, P. Hubler, R. Stephan, D. Greenlaw, M. Raab, N. Kepler, H. Chen, D. Chidambarrao, D. Fried, J. Holt, W. Lee, H. Nii, S. Panda, T. Sato, A. Waite, S. Liming, K. Rim, D. Schepis, M. Khare, S. Huang, J. Pellerin, L. T. Su
{"title":"Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies","authors":"M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, T. Feudel, K. Frohberg, M. Gerhardt, A. Hellmich, K. Hempel, J. Hohage, P. Javorka, J. Klais, G. Koerner, M. Lenski, A. Neu, R. Otterbach, P. Press, C. Reichel, M. Trentsch, B. Trui, H. Salz, M. Schaller, H. Engelmann, O. Herzog, H. Ruelke, P. Hubler, R. Stephan, D. Greenlaw, M. Raab, N. Kepler, H. Chen, D. Chidambarrao, D. Fried, J. Holt, W. Lee, H. Nii, S. Panda, T. Sato, A. Waite, S. Liming, K. Rim, D. Schepis, M. Khare, S. Huang, J. Pellerin, L. T. Su","doi":"10.1109/IEDM.2005.1609315","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609315","url":null,"abstract":"An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS \"stressors\"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS \"stressors\"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD's 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"70 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77922639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Performance of carbon nanotube field effect transistors with doped source and drain extensions and arbitrary geometry 掺杂源极扩展和任意几何形状的碳纳米管场效应晶体管的性能
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609397
G. Fiori, G. Iannaccone, Gerhard Klimeck
{"title":"Performance of carbon nanotube field effect transistors with doped source and drain extensions and arbitrary geometry","authors":"G. Fiori, G. Iannaccone, Gerhard Klimeck","doi":"10.1109/IEDM.2005.1609397","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609397","url":null,"abstract":"In this work, we investigate the expected device performance and the scaling perspectives of carbon nanotube field effect transistors (CNT-FETs), with doped source and drain extensions, by means of a novel three-dimensional NEGF-based simulation tool capable of considering arbitrary gate geometry and device architecture. In particular, we have investigated short channel effects for different gate configurations and geometry parameters. Double gate devices offer quasi ideal subthreshold slope and DIBL also with not extremely thin gate dielectrics. In addition, we show that devices with parallel CNTs can provide On currents per unit width significantly larger than their silicon counterpart, and that high-frequency performance is very promising","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"13 1","pages":"522-525"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78365813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
High performance nanocrystalline-Si TFT fabricated at 150/spl deg/ C using ICP-CVD 用ICP-CVD在150/spl℃下制备高性能纳米晶硅TFT
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609282
Sang-Myeon Han, Joonghyun Park, Hee‐Sun Shin, Young-Hwan Choi, M. Han
{"title":"High performance nanocrystalline-Si TFT fabricated at 150/spl deg/ C using ICP-CVD","authors":"Sang-Myeon Han, Joonghyun Park, Hee‐Sun Shin, Young-Hwan Choi, M. Han","doi":"10.1109/IEDM.2005.1609282","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609282","url":null,"abstract":"Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) were fabricated using ICP-CVD at 150degC. The fabricated nc-Si TFT exhibits high field effect mobility exceeding 22cm2/Vs and a low sub-threshold slope of 0.45V/dec. The nc-Si film deposited 150degC as an active layer of the TFT shows good crystallinity more than 70% and the gate insulator SiO2 film deposited by ICP-CVD at 150degC shows good electrical characteristics such as flat band voltage of -1.8V and breakdown voltage of 6.2MV/cm","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"1 1","pages":"117-120"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78427523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories 双位离散陷阱非易失性存储器缩放问题的实验与理论分析
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609492
L. Perniola, G. Iannaccone, B. De Salvo, G. Ghibaudo, G. Molas, C. Gerardi, S. Deleonibust
{"title":"Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories","authors":"L. Perniola, G. Iannaccone, B. De Salvo, G. Ghibaudo, G. Molas, C. Gerardi, S. Deleonibust","doi":"10.1109/IEDM.2005.1609492","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609492","url":null,"abstract":"Here we present an experimental and theoretical analysis of dual-bit DT-NVMs. In particular data retention experiments on bulk and SOI silicon nanocrystal memory devices and their interpretation through a surface potential based model are shown (Perniola et al., 2005). Our model is then exploited to investigate the main issues posed by dual-bit reading, when the dimensions of bulk and SOI devices are scaled down. We present two different reading schemes for a scaled device and we show that dual-bit performance of DT-NVMs, charged on both sides, is preserved even when the two pockets of charge coalesce. Finally, we conclude that both bulk and SOI dual-bit architectures are promising for memory cells with gate lengths down to 30-50 nm","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"21 1","pages":"857-860"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74745515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Highly efficient current scaling AMOLED panel employing a new current mirror pixel circuit fabricated by excimer laser annealed poly-Si TFTs 采用准分子激光退火多晶硅tft制备的新型电流镜像像素电路的高效电流缩放AMOLED面板
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609512
Jae-Hoon Lee, W. Nam, Hee‐Sun Shin, M. Han, Yong‐Min Ha, ChangHwa Lee, Hong-Seok Choi, Soon‐Kwang Hong
{"title":"Highly efficient current scaling AMOLED panel employing a new current mirror pixel circuit fabricated by excimer laser annealed poly-Si TFTs","authors":"Jae-Hoon Lee, W. Nam, Hee‐Sun Shin, M. Han, Yong‐Min Ha, ChangHwa Lee, Hong-Seok Choi, Soon‐Kwang Hong","doi":"10.1109/IEDM.2005.1609512","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609512","url":null,"abstract":"We propose and fabricate highly efficient current scaling AMOLED panel employing excimer laser annealed poly-Si TFTs, which successfully compensate the non-uniformity of IOLED due to the grain boundaries and residual image caused by a hysteresis phenomenon in poly-Si TFT. The proposed 2.4 inch panel employing a new current mirror pixel circuit successfully reduces a nonuniformity of the luminance from 41% to 9.1%, and eliminates residual image, compared with conventional 2-TFT pixel array. The proposed pixel circuit can also increase the data current by 57% and decrease the pixel charging time by 21%, compared with a traditional current mirror pixel","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"125 1","pages":"931-934"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74478802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Light emitting silicon nanostructures 发光硅纳米结构
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609531
L. Dal Negro, J. H. Yi, M. Stolfi, J. Michel, J. LeBlanc, J. Haavisto, L. Kimerling
{"title":"Light emitting silicon nanostructures","authors":"L. Dal Negro, J. H. Yi, M. Stolfi, J. Michel, J. LeBlanc, J. Haavisto, L. Kimerling","doi":"10.1109/IEDM.2005.1609531","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609531","url":null,"abstract":"In this paper the main results on the energy sensitization and optical properties of light-emitting silicon based nanostructures for microphotonics applications are reviewed. The energy sensitization of erbium ions from silicon nanocrystals embedded in silicon-rich oxide (SRO) and silicon-rich nitride matrices (SRN) are discussed. For both the systems the efficient energy transfer to erbium ions is demonstrated. In addition, it is shown that SRN is a suitable material for the fabrication of optically active complex photonic crystal structures","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"4 pp.-1000"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72607453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信