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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.最新文献

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85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications 85nm栅极长度增强和耗尽模式InSb量子阱晶体管，用于超高速和极低功耗数字逻辑应用
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609466
S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, D. Wallis, P. Wilding, R. Chau
{"title":"85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications","authors":"S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, D. Wallis, P. Wilding, R. Chau","doi":"10.1109/IEDM.2005.1609466","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609466","url":null,"abstract":"We demonstrate for the first time 85nm gate length enhancement and depletion mode InSb quantum well transistors with unity gain cutoff frequency, fT, of 305 GHz and 256 GHz, respectively, at 0.5V VDS, suitable for high speed, very low power logic applications. The InSb transistors demonstrate 50% higher unity gain cutoff frequency, fT, than silicon NMOS transistors while consuming 10 times less active power","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"62 1","pages":"763-766"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88290944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 146
Physics-based noise modelling of semiconductor devices in largesignal operation including low-frequency noise conversion effects 包括低频噪声转换效应在内的半导体器件大信号工作中基于物理的噪声建模
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609309
G. Ghione, F. Bonani, S. Donati, F. Bertazzi, G. Conte
{"title":"Physics-based noise modelling of semiconductor devices in largesignal operation including low-frequency noise conversion effects","authors":"G. Ghione, F. Bonani, S. Donati, F. Bertazzi, G. Conte","doi":"10.1109/IEDM.2005.1609309","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609309","url":null,"abstract":"A review is provided on state-of-the-art techniques for the physics-based numerical simulation of noise in semiconductor devices, with particular attention to large-signal forced operation and to the related noise frequency conversion. Open problems associated to the modeling of 1/f-like noise in large-signal operation through a superposition of GR noise sources are discussed with the help of simulation examples. Finally, a 2D physics-based noise analysis of a FET active mixer is presented","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"22 1","pages":"212-215"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86501504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications 用于系统面板(SoP)应用的0.1/spl mu/m多晶硅薄膜晶体管
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609507
B. Tsui, Chia-Pin Lin, Chih-Feng Huang, Y. Xiao
{"title":"0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications","authors":"B. Tsui, Chia-Pin Lin, Chih-Feng Huang, Y. Xiao","doi":"10.1109/IEDM.2005.1609507","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609507","url":null,"abstract":"Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mum channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"259 1","pages":"911-914"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86331678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram 一种具有自旋转矩传递磁化开关的新型非易失性存储器:自旋ram
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609379
M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, Hiroshi Kano
{"title":"A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram","authors":"M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, Hiroshi Kano","doi":"10.1109/IEDM.2005.1609379","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609379","url":null,"abstract":"A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time. The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM. This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm. The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure. The 4kbit spin-RAM was fabricated on a 4 level metal, 0.18 mum CMOS process. In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated. It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"248 1","pages":"459-462"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82880156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 774
An easily integrable NiSi TOSI-gate/SiON-module for LP SRAM applications based on a single step silicidation of gate and junction 一种易于集成的NiSi tosi门/ sion模块，用于LP SRAM应用，基于门和结的单步硅化
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609428
M. Muller, A. Mondot, N. Gierczynski, D. Aimé, B. Froment, F. Leverd, P. Gouraud, A. Talbot, S. Descombes, Y. Morand, Y. Le Tiec, P. Besson, A. Toffoli, G. Ribes, J. Roux, S. Pokrant, F. Andre, T. Skotnicki
{"title":"An easily integrable NiSi TOSI-gate/SiON-module for LP SRAM applications based on a single step silicidation of gate and junction","authors":"M. Muller, A. Mondot, N. Gierczynski, D. Aimé, B. Froment, F. Leverd, P. Gouraud, A. Talbot, S. Descombes, Y. Morand, Y. Le Tiec, P. Besson, A. Toffoli, G. Ribes, J. Roux, S. Pokrant, F. Andre, T. Skotnicki","doi":"10.1109/IEDM.2005.1609428","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609428","url":null,"abstract":"In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"281 2 1","pages":"626-629"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86640597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-voltage LDMOS compact model for RF applications 用于射频应用的高压LDMOS紧凑型模型
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609308
M. Willemsen, R. Van Langevelde
{"title":"High-voltage LDMOS compact model for RF applications","authors":"M. Willemsen, R. Van Langevelde","doi":"10.1109/IEDM.2005.1609308","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609308","url":null,"abstract":"We present a compact model for RF-LDMOS transistors. The model is based on a continuous description of the lateral electric field, and contains the physical phenomena of partial lateral depletion and velocity saturation in the drift region. The model has been validated with device simulations and measurements","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"2 1","pages":"208-211"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91527253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed 新型过渡层设计的MHSOS结构硅纳米晶闪存具有大的V/sub /窗口和快速的P/E速度
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609494
K. Joo, Xiofeng Wang, J. Han, Seung-Hyun Lim, Seungjae Baik, Yong-Won Cha, Jin-Wook Lee, I. Yeo, Y. Cha, I. Yoo, U. Chung, J. Moon, B. Ryu
{"title":"Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed","authors":"K. Joo, Xiofeng Wang, J. Han, Seung-Hyun Lim, Seungjae Baik, Yong-Won Cha, Jin-Wook Lee, I. Yeo, Y. Cha, I. Yoo, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2005.1609494","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609494","url":null,"abstract":"In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"43 1","pages":"4 pp.-868"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83249506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Robust multi-bit programmable flash memory using a resonant tunnel barrier 稳健的多比特可编程闪存使用谐振隧道屏障
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609493
S. Kim, Seungjae Baik, Z. Huo, Y. Noh, Chul-Sung Kim, J. Han, I. Yeo, U. Chung, J. Moon, B. Ryu
{"title":"Robust multi-bit programmable flash memory using a resonant tunnel barrier","authors":"S. Kim, Seungjae Baik, Z. Huo, Y. Noh, Chul-Sung Kim, J. Han, I. Yeo, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2005.1609493","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609493","url":null,"abstract":"A novel multi-bit flash memory using a SiO2/a-Si/SiO 2 resonant tunnel barrier was fabricated for the first time. The SONOS-type memory with a resonant tunnel barrier is programmed only at preferential bias conditions determined by quantum tunneling conditions. By doing so, the dispersion of multi-level programmed threshold voltages, Vth, are drastically reduced, and highly reliable data storage is possible. Moreover, program/erase speed, data retention, endurance and read disturb characteristics were also shown to be better than that of a conventional SiO2 tunnel barrier","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"185 1","pages":"861-864"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83441508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm 导电桥接RAM (CBRAM):一种新兴的可扩展到20nm以下的非易失性存储技术
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609463
M. Kund, Gerhard Beitel, C. Pinnow, Thomas Röhr, Jörg Schumann, R. Symanczyk, K. Ufert, Gerhard Müller
{"title":"Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm","authors":"M. Kund, Gerhard Beitel, C. Pinnow, Thomas Röhr, Jörg Schumann, R. Symanczyk, K. Ufert, Gerhard Müller","doi":"10.1109/IEDM.2005.1609463","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609463","url":null,"abstract":"We report on the electrical characterisation of nanoscale conductive bridging memory cells, composed of a thin solid state electrolyte layer sandwiched between an oxidizable anode and an inert cathode. Low power resistive switching operation, the large scalability potential including multi-level-capability (MLC) and the investigated reliability aspects, like retention at elevated temperature, operating temperature and endurance, make CBRAM a very promising non-volatile emerging memory technology","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"23 1","pages":"754-757"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83491906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 263
A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT) 一种新型的薄电容耦合晶闸管(TCCT)无电容DRAM电池
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609337
Hyun-jin Cho, F. Nemati, R. Roy, R. Gupta, K. Yang, M. Ershov, S. Banna, M. Tarabbia, C. Sailing, D. Hayes, A. Mittal, S. Robins
{"title":"A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)","authors":"Hyun-jin Cho, F. Nemati, R. Roy, R. Gupta, K. Yang, M. Ershov, S. Banna, M. Tarabbia, C. Sailing, D. Hayes, A. Mittal, S. Robins","doi":"10.1109/IEDM.2005.1609337","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609337","url":null,"abstract":"A capacitor-less DRAM cell using a thin capacitively-coupled thyristor (TCCT DRAM) is introduced. Experimental results from unit memory cell fabricated in a 130nm SOI logic technology demonstrate Ion/Ioff ratio of 107, non-destructive read; write speed less than 2ns at 125C, and solid retention characteristics. These cell characteristics combined with a small cell area (as low as 9F2) and simple process integration make TCCT DRAM a suitable candidate for high-performance high-density embedded or standalone memory applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"77 1","pages":"311-314"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84655405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
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