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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.最新文献

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High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique 45纳米的高性能CMOSFET技术和应力诱导迁移增强技术的可扩展性
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2006-01-13 DOI: 10.1109/IEDM.2005.1609314
A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, L. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima, F. Matsuoka
{"title":"High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique","authors":"A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, L. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima, F. Matsuoka","doi":"10.1109/IEDM.2005.1609314","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609314","url":null,"abstract":"High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for 45nm technology CMOSFET. It is confirmed that the stress enhancement factors using multiple booster techniques remain valid, which proves that these techniques are scalable for future technology","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"127 6 1","pages":"229-232"},"PeriodicalIF":0.0,"publicationDate":"2006-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83653610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor 一种新型兼容CMOS的l形冲击电离MOS晶体管
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609518
E. Toh, G. Wang, G. Lo, N. Balasubramanian, C. Tung, F. Benistant, L. Chan, G. Samudra, Y. Yeo
{"title":"A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor","authors":"E. Toh, G. Wang, G. Lo, N. Balasubramanian, C. Tung, F. Benistant, L. Chan, G. Samudra, Y. Yeo","doi":"10.1109/IEDM.2005.1609518","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609518","url":null,"abstract":"This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor technology that achieves subthreshold swing well below 60 mV/decade at room temperature. First, the LI-MOS transistor is CMOS process compatible, and requires little process modification for integration in a manufacturable process. Second, the LI-MOS structure employs raised source/drain (S/D) regions that enable controllability and scalability of the impact ionization region (I-region). Third, the LI-MOS has superior compactness over previously reported I-MOS device structures. Fourth, the LI-MOS enables the integration of novel materials for band gap and strain engineering to enhance the impact ionization rate in the I-region. Based on the above technology, we demonstrate a record subthreshold swing of 4.5 mV/decade at room temperature for a 100 run gate length device that incorporates a SiGe I-region. The smallest impact-ionization-based MOS device with a gate length of 60 nm is also demonstrated with a subthreshold swing that is well below 60 mV/decade","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"1148 1","pages":"951-954"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73562260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Ge-spacer technology in AlGaN/GaN HEMTs for mm-wave applications 用于毫米波应用的AlGaN/GaN hemt中的ge间隔技术
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609472
T. Palacios, E. Snow, Y. Pei, A. Chakraborty, S. Keller, S. Denbaars, U. Mishra
{"title":"Ge-spacer technology in AlGaN/GaN HEMTs for mm-wave applications","authors":"T. Palacios, E. Snow, Y. Pei, A. Chakraborty, S. Keller, S. Denbaars, U. Mishra","doi":"10.1109/IEDM.2005.1609472","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609472","url":null,"abstract":"GaN-based high electron mobility transistors (HEMTs) are the most promising option for power amplification at frequencies above 30 GHz. However, the difficult technology of nitride devices has hindered the aggressive scaling of these transistors needed for high frequency applications. Also, the need of a relatively thick passivation layer to avoid current collapse in these transistors has significantly limited the high frequency performance of the devices. In this paper, we introduces an advanced technology which uses a Ge sacrificial layer to fabricate passivated AlGaN/GaN HEMTs with gate lengths down to 90 nm, while maintaining a high breakdown voltage and minimum parasitic capacitances. Using these devices, we demonstrate record high frequency performance at both small and large signal levels","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"113 1","pages":"3 pp.-789"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75798311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Low-voltage inkjetted organic transistors for printed RFID and display applications 用于印刷RFID和显示应用的低压喷墨有机晶体管
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609280
S. Molesa, A. de la Fuente Vornbrock, P. Chang, V. Subramanian
{"title":"Low-voltage inkjetted organic transistors for printed RFID and display applications","authors":"S. Molesa, A. de la Fuente Vornbrock, P. Chang, V. Subramanian","doi":"10.1109/IEDM.2005.1609280","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609280","url":null,"abstract":"We demonstrate printed organic transistors with sub-10V VDD . Using inkjetted nanoparticle conductors, a polymer dielectric, and a pentacene precursor semiconductor, we demonstrate devices on plastic with mobilities >0.05cm2/V-s and on-off ratios >105. Thus, for the first time, we demonstrate devices with operating specifications approaching those required for low-cost electronic systems","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"27 1","pages":"109-112"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74781730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A 28 mega pixel large area full frame CCD with 2/spl times/2 on-chip RGB charge-binning for professional digital still imaging 2800万像素大面积全画幅CCD, 2/spl倍/2片上RGB充电，用于专业数码静止成像
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609478
C. Draijer, F. Polderdijk, A. van der Heide, B. Dillen, W. Klaassens, J. Bosiers
{"title":"A 28 mega pixel large area full frame CCD with 2/spl times/2 on-chip RGB charge-binning for professional digital still imaging","authors":"C. Draijer, F. Polderdijk, A. van der Heide, B. Dillen, W. Klaassens, J. Bosiers","doi":"10.1109/IEDM.2005.1609478","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609478","url":null,"abstract":"CCD imagers for professional digital still cameras (DSCs) require in general high resolution. However for some applications, high sensitivity and high speed are more important and can be exchanged for resolution. A concept is presented in which the resolution of the imager will be decreased in binning mode while the sensitivity and frame rates are increased. For color CCDs, the RGB Bayer color filter pattern should be preserved after charge binning without discarding charge. The first results of this new concept are presented","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"7 1","pages":"4 pp.-810"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84316291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with <100> uni-axial and [100] uni-plane channels 通过采用具有单轴和[100]单平面通道的直凹槽通道阵列晶体管克服DRAM的缩放限制
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609339
I. Kim, S. Park, J. Yoon, D. Kim, J.Y. Noh, J. Lee, Y. Kim, M. Hwang, K. Yang, Joosung Park, Kyungseok Oh
{"title":"Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with <100> uni-axial and [100] uni-plane channels","authors":"I. Kim, S. Park, J. Yoon, D. Kim, J.Y. Noh, J. Lee, Y. Kim, M. Hwang, K. Yang, Joosung Park, Kyungseok Oh","doi":"10.1109/IEDM.2005.1609339","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609339","url":null,"abstract":"Recessed channel array transistors (RCAT) for DRAM are implemented with <100> uni-axial and {100} uni-plane channels for the first time. It is found that this structure improves the cell transistor drivability by 25% with the improvement being more effective in straight shape active RCAT than the diagonal shape active RCAT due to the larger dimension of the horizontal <100> axial channel in the {100} plane. Enhanced RCAT drivability improves tRDL (allowed time interval between data-in and word-line precharge) and retention time, which allows for lowering the gate voltage over-drive (VPP) in DRAM operation. This possibility provides a breakthrough in reliability limitations and leads to better performance in nano-scaled DRAM","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"3 1","pages":"319-322"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85005142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-speed blue-, red-, and infrared-sensitive photodiode integrated in a 0.35 /spl mu/m SiGe:C-BiCMOS process 高速蓝、红、红外敏感光电二极管集成在0.35 /spl μ m SiGe:C-BiCMOS工艺
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609477
G. Meinhardt, J. Kraft, B. Loffler, H. Enichlmair, G. Rohrer, E. Wachmann, M. Schrems, R. Swoboda, C. Seidl, H. Zimmermann
{"title":"High-speed blue-, red-, and infrared-sensitive photodiode integrated in a 0.35 /spl mu/m SiGe:C-BiCMOS process","authors":"G. Meinhardt, J. Kraft, B. Loffler, H. Enichlmair, G. Rohrer, E. Wachmann, M. Schrems, R. Swoboda, C. Seidl, H. Zimmermann","doi":"10.1109/IEDM.2005.1609477","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609477","url":null,"abstract":"A monolithically integrated photodiode with SiGe:C anode, which exhibits an excellent spectral responsivity of typically 0.21/0.42/0.53 A/W at 410/660/785nm and sub-ns rise/fall times, fabricated without process modification is presented. The bandwidth of the photodiode exceeds 1300/490/260MHz at 410/660/785nm favoring this device for universal optical storage applications. By applying a reverse bias voltage up to 10 V the photodiode features responsivities up to 0.6 A/W for 410nm due to avalanche multiplication","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"77 1","pages":"803-806"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76627938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dislocation engineering for a silicon-based light emitter at 1.5 /spl mu/ 1.5 /spl μ /硅基光发射器的位错工程
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609533
M. Kittler, M. Reiche, T. Arguirov, W. Seifert, X. Yu
{"title":"Dislocation engineering for a silicon-based light emitter at 1.5 /spl mu/","authors":"M. Kittler, M. Reiche, T. Arguirov, W. Seifert, X. Yu","doi":"10.1109/IEDM.2005.1609533","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609533","url":null,"abstract":"A new concept for a Si light emitting diode (LED) capable of emitting at 1.5 mum efficiently is proposed. It utilizes radiation from a well-defined dislocation network created in a reproducible manner by Si wafer direct bonding. The wavelength of the light emitted from the network can be tailored by adjusting the misorientation between the Si wafers","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"97 1","pages":"1005-1008"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73599325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Wrap-gated inas nanowire field-effect transistor 包裹门控纳米线场效应晶体管
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609324
L. Wernersson, T. Bryllert, E. Lind, L. Samuelson
{"title":"Wrap-gated inas nanowire field-effect transistor","authors":"L. Wernersson, T. Bryllert, E. Lind, L. Samuelson","doi":"10.1109/IEDM.2005.1609324","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609324","url":null,"abstract":"Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds equiv 0.15 V (for Vg equiv 0 V) and low voltage operation Vth equiv -0.15 V, and present opportunities to improve the device performance by heterostructure design","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"38 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72849952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS 基于45nm块体CMOS激光退火的高密度高速SRAM位单元和环形振荡器
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609438
A. Pouydebasque, B. Dumont, S. Denorme, F. Wacquant, M. Bidaud, C. Laviron, A. Halimaoui, C. Chaton, J. Chapon, P. Gouraud, F. Leverd, H. Bernard, S. Warrick, D. Delille, K. Romanjek, R. Gwoziecki, N. Planes, S. Vadot, I. Pouilloux, F. Arnaud, F. Boeuf, T. Skotnicki
{"title":"High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS","authors":"A. Pouydebasque, B. Dumont, S. Denorme, F. Wacquant, M. Bidaud, C. Laviron, A. Halimaoui, C. Chaton, J. Chapon, P. Gouraud, F. Leverd, H. Bernard, S. Warrick, D. Delille, K. Romanjek, R. Gwoziecki, N. Planes, S. Vadot, I. Pouilloux, F. Arnaud, F. Boeuf, T. Skotnicki","doi":"10.1109/IEDM.2005.1609438","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609438","url":null,"abstract":"In this work, we report on the integration of 30nm gate length CMOS devices fabricated using laser spike annealing (LSA). Considerably improved short channel effects and drive current (+10% I<sub>on</sub> at constant I<sub>off</sub> for NMOS) are demonstrated on samples using LSA. Excellent I<sub>on</sub>I<sub>off</sub> characteristics (I<sub>on </sub> = 940 muA/mum I<sub>off</sub> = 200 muA/mum for NMOS and I<sub>on</sub> = 390muA/mum I<sub>off</sub> = 50 nA/mum for PMOS at V<sub>dd</sub> = 1 V) are measured that are at the leading edge of the state of the art. Moreover, an enhanced dynamic behavior (-6% in ring oscillator delay) and improved characteristics of high density SRAM bit-cells (+24% I<sub>cell</sub> for the same 1<sub>sb</sub>) are reported. These results demonstrate the potential of LSA in the perspective of 30 nm device integration of a 45 nm bulk CMOS platform","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"35 1","pages":"663-666"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87985330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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