High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2006-01-13 DOI:10.1109/IEDM.2005.1609314

A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, L. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima, F. Matsuoka

{"title":"High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique","authors":"A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, L. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima, F. Matsuoka","doi":"10.1109/IEDM.2005.1609314","DOIUrl":null,"url":null,"abstract":"High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for 45nm technology CMOSFET. It is confirmed that the stress enhancement factors using multiple booster techniques remain valid, which proves that these techniques are scalable for future technology","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"127 6 1","pages":"229-232"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609314","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 45

Abstract

High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for 45nm technology CMOSFET. It is confirmed that the stress enhancement factors using multiple booster techniques remain valid, which proves that these techniques are scalable for future technology

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45纳米的高性能CMOSFET技术和应力诱导迁移增强技术的可扩展性

演示了45纳米一代的高性能CMOSFET技术。讨论了结缩尺、栅极堆缩尺和应力诱导迁移率增强的关键器件策略。反序结的形成大大改善了短通道效应。改进了多晶硅栅极损耗的新型硅离子使驱动电流提高了8%。对工艺诱导的迁移率增强进行了系统的研究，证实了eSiGe和应力衬垫技术等新方案适用于45nm工艺的CMOSFET。研究证实，使用多种助推技术的应力增强系数仍然有效，这证明了这些技术在未来的技术中是可扩展的

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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