K. Joo, Xiofeng Wang, J. Han, Seung-Hyun Lim, Seungjae Baik, Yong-Won Cha, Jin-Wook Lee, I. Yeo, Y. Cha, I. Yoo, U. Chung, J. Moon, B. Ryu
{"title":"新型过渡层设计的MHSOS结构硅纳米晶闪存具有大的V/sub /窗口和快速的P/E速度","authors":"K. Joo, Xiofeng Wang, J. Han, Seung-Hyun Lim, Seungjae Baik, Yong-Won Cha, Jin-Wook Lee, I. Yeo, Y. Cha, I. Yoo, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2005.1609494","DOIUrl":null,"url":null,"abstract":"In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"43 1","pages":"4 pp.-868"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed\",\"authors\":\"K. Joo, Xiofeng Wang, J. Han, Seung-Hyun Lim, Seungjae Baik, Yong-Won Cha, Jin-Wook Lee, I. Yeo, Y. Cha, I. Yoo, U. Chung, J. Moon, B. Ryu\",\"doi\":\"10.1109/IEDM.2005.1609494\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization\",\"PeriodicalId\":13071,\"journal\":{\"name\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"volume\":\"43 1\",\"pages\":\"4 pp.-868\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2005.1609494\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609494","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed
In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization