Hyun-jin Cho, F. Nemati, R. Roy, R. Gupta, K. Yang, M. Ershov, S. Banna, M. Tarabbia, C. Sailing, D. Hayes, A. Mittal, S. Robins
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A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)
A capacitor-less DRAM cell using a thin capacitively-coupled thyristor (TCCT DRAM) is introduced. Experimental results from unit memory cell fabricated in a 130nm SOI logic technology demonstrate Ion/Ioff ratio of 107, non-destructive read; write speed less than 2ns at 125C, and solid retention characteristics. These cell characteristics combined with a small cell area (as low as 9F2) and simple process integration make TCCT DRAM a suitable candidate for high-performance high-density embedded or standalone memory applications
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