Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI:10.1109/IEDM.2005.1609315

M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, T. Feudel, K. Frohberg, M. Gerhardt, A. Hellmich, K. Hempel, J. Hohage, P. Javorka, J. Klais, G. Koerner, M. Lenski, A. Neu, R. Otterbach, P. Press, C. Reichel, M. Trentsch, B. Trui, H. Salz, M. Schaller, H. Engelmann, O. Herzog, H. Ruelke, P. Hubler, R. Stephan, D. Greenlaw, M. Raab, N. Kepler, H. Chen, D. Chidambarrao, D. Fried, J. Holt, W. Lee, H. Nii, S. Panda, T. Sato, A. Waite, S. Liming, K. Rim, D. Schepis, M. Khare, S. Huang, J. Pellerin, L. T. Su

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引用次数: 61

Abstract

An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD's 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing

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集成和优化嵌入sige，压缩和拉伸应力衬垫薄膜，并在先进的SOI CMOS技术的应力记忆

提出了一种优化的部分耗尽型SOI (PD-SOI) CMOS上的4路应力集成方法。采用嵌入式sige工艺和压应力衬垫膜来诱导PMOS中的压应变(PMOS“应力源”)。在NMOS (NMOS“应力源”)中使用应力记忆过程和拉伸应力衬垫膜来诱导拉伸应变。通过优化，不同的应力技术具有高度的相容性和叠加性，PMOS和NMOS的饱和驱动电流分别提高了53%和32%。这种改进使产品速度提高了40%。为了证明未来晶体管节点的可扩展性，应力改进进一步增加，导致PMOS性能在200nA IOFF(自加热校正)和1V时达到创纪录的IDSAT=860muA/mum。应力技术已在AMD的90纳米制造工艺中得到验证，并已扩展到65纳米制造中

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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