用于高迁移率双通道CMOS的高k/金属栅极堆叠应变Si和Ge mosfet

Olivier Weber, Y. Bogumilowicz, Thomas Ernst, J. Hartmann, F. Ducroquet, F. Andrieu, Cecilia Dupre, L. Clavelier, C. L. Royer, Nikolay Cherkashin, Martin Hÿtch, D. Rouchon, H. Dansas, A. Papon, V. Carron, C. Tabone, S. Deleonibus
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引用次数: 29

摘要

采用相同的工艺制备了具有TiN/HfO2栅极堆叠的外延应变Si和Ge n-和p- mosfet,用于双通道集成方案。与HfO2/Si基准相比,X1.7应变Si电子和X9应变Ge空穴迁移率提高,实现了对称的n-和p-MOSFET IDsat性能。这种X9应变Ge空穴迁移率的增强大大超过了先前报道的高k介电体Ge pmosfet的结果。这是第一次用薄的高k栅极电介质(EOT=14Aring)证明了这种空穴迁移率的增强,理论预测和实验报道了厚SiO2栅极电介质。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS
Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the same process for a dual channel integration scheme. Compared to the HfO2/Si reference, X1.7 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET IDsat performance. This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics. For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO2 gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)
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