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An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control 一种带门控时钟调节环和浪涌电流控制的无源超高频RFID应答器的EEPROM编程控制器
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405760
R. Barnett, Jin Liu
{"title":"An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control","authors":"R. Barnett, Jin Liu","doi":"10.1109/CICC.2007.4405760","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405760","url":null,"abstract":"This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. It generates a 14 V programming voltage for a 224-bit EEPROM memory array from a rectified voltage supply of 2-3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write-erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of Meg-ohm resistors needed for nano-power operation. Measurement results show that a 0.35 mum CMOS transponder IC provides a stable 14 V EEPROM programming voltage and consumes only 7 muW during write operation. The EEPROM programming controller occupies 0.092 mm2 die area.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
CAD Techniques for Power Optimization in Virtex-5 FPGAs Virtex-5 fpga电源优化的CAD技术
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405687
Subodh Gupta, J. Anderson, L. Farragher, Qiang Wang
{"title":"CAD Techniques for Power Optimization in Virtex-5 FPGAs","authors":"Subodh Gupta, J. Anderson, L. Farragher, Qiang Wang","doi":"10.1109/CICC.2007.4405687","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405687","url":null,"abstract":"We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124372066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
3D Capacitive Interconnections for High Speed Interchip Communication 高速芯片间通信的三维电容互连
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405670
R. Canegallo, A. Fazzi, L. Ciccarelli, L. Magagni, F. Natali, P. Rolandi, E. Jung, L. Cioccio, R. Guerrieri
{"title":"3D Capacitive Interconnections for High Speed Interchip Communication","authors":"R. Canegallo, A. Fazzi, L. Ciccarelli, L. Magagni, F. Natali, P. Rolandi, E. Jung, L. Cioccio, R. Guerrieri","doi":"10.1109/CICC.2007.4405670","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405670","url":null,"abstract":"A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts 基于最坏情况感知pareto最优前沿的SC ΣΔ调制器优化
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405805
J. Zou, H. Graeb, D. Mueller, Ulf Schlichtmann
{"title":"Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts","authors":"J. Zou, H. Graeb, D. Mueller, Ulf Schlichtmann","doi":"10.1109/CICC.2007.4405805","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405805","url":null,"abstract":"This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. the Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124232526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Active CMOS Array for Electrochemical Sensing of Biomolecules 生物分子电化学传感的有源CMOS阵列
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405855
P. Levine, P. Gong, K. Shepard, R. Levicky
{"title":"Active CMOS Array for Electrochemical Sensing of Biomolecules","authors":"P. Levine, P. Gong, K. Shepard, R. Levicky","doi":"10.1109/CICC.2007.4405855","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405855","url":null,"abstract":"We describe the design of a 4times4 active sensor array for multiplexed electrochemical biomolecular detection in a 0.25-mum-CMOS process. Integrated potentiostats sense the current flowing through the on-chip Au electrodes that result from reactions occurring at the chip surface. Preliminary experimental results include cyclic voltammetry of several redox species and application to DNA probe coverage characterization.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117146294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing 利用异或阵列(VPEX)实现EB直写的可编程逻辑结构
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405728
Akihiro Nakamura, Masahide Kawaharazaki, M. Yoshikawa, T. Fujino
{"title":"Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing","authors":"Akihiro Nakamura, Masahide Kawaharazaki, M. Yoshikawa, T. Fujino","doi":"10.1109/CICC.2007.4405728","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405728","url":null,"abstract":"In this paper, we propose the novel architecture of VCLD (via configurable logic device) called VPEX (via programmable logic using exclusive-OR array) which is optimized for electron beam (EB) direct writing. The logic element (LE) of VPEX consists of complex gate type exclusive OR (EXOR) and inverter (NOT) gates. The single LE can output 12 logics which include all 2-inputs logic functions (NAND, NOR AND, OR bubble AND, bubble OR XOR XNOR), 3 inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout. Scan D-FlipFlop can be composed by using 5 LEs. The logic of each LE can be defined by double EB exposure using \"character beam\". The speed performance of VPEX is much better than that of FPGAs, and 1.5 times worse than that of ASICs. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115710397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Cell Broadband Engine Processor Design Methodology 蜂窝宽带引擎处理器设计方法
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405830
O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. P. Hofstee, C. J. Johnson, S. Posluszny
{"title":"Cell Broadband Engine Processor Design Methodology","authors":"O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. P. Hofstee, C. J. Johnson, S. Posluszny","doi":"10.1109/CICC.2007.4405830","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405830","url":null,"abstract":"The cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115745912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Towards a sub-2.5V, 100-Gb/s Serial Transceiver 迈向2.5 v以下，100gb /s串行收发器
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405776
S. Voinigescu, R. Aroca, T. Dickson, S. Nicolson, T. Chalvatzis, P. Chevalier, P. Garcia, C. Gamier, B. Sautreuil
{"title":"Towards a sub-2.5V, 100-Gb/s Serial Transceiver","authors":"S. Voinigescu, R. Aroca, T. Dickson, S. Nicolson, T. Chalvatzis, P. Chevalier, P. Garcia, C. Gamier, B. Sautreuil","doi":"10.1109/CICC.2007.4405776","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405776","url":null,"abstract":"This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100degC. Inductor and transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130806596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A Process and Temperature Compensated Two-Stage Ring Oscillator 一种过程和温度补偿两级环形振荡器
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405826
K. Lakshmikumar, Vinod Mukundagiri, S. Gierkink
{"title":"A Process and Temperature Compensated Two-Stage Ring Oscillator","authors":"K. Lakshmikumar, Vinod Mukundagiri, S. Gierkink","doi":"10.1109/CICC.2007.4405826","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405826","url":null,"abstract":"Local positive feedback in a delay element enables a ring oscillator with only two stages to oscillate and produce quadrature clocks. Routh-Hurwitz's criterion is applied to prove that such a structure can oscillate. An internally generated power supply from a constant-gm bias keeps the free running frequency to within plusmn 5% from -40 to 125degC over process variations. The 1.25 GHz oscillator in 0.13 mum CMOS draws 3.4 mA and has a phase noise of -88 dBc/Hz at 1MHz offset.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131304315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Evolution of CMOS Technology at 32 nm and Beyond 32纳米及以上CMOS技术的发展
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405764
G. Shahidi
{"title":"Evolution of CMOS Technology at 32 nm and Beyond","authors":"G. Shahidi","doi":"10.1109/CICC.2007.4405764","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405764","url":null,"abstract":"Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. Chip power has been increasing rapidly, approaching air cool limit. Power limit is transforming CMOS scaling to more of a density driver. As we move to 32 nm node and beyond a number of additional fundamental challenges are faced, which may force additional rethinking of how scaling has been done. This paper is an overview of some upcoming challenges and possible ways of addressing them.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126390229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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