O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. P. Hofstee, C. J. Johnson, S. Posluszny
{"title":"Cell Broadband Engine Processor Design Methodology","authors":"O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. P. Hofstee, C. J. Johnson, S. Posluszny","doi":"10.1109/CICC.2007.4405830","DOIUrl":null,"url":null,"abstract":"The cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.