Towards a sub-2.5V, 100-Gb/s Serial Transceiver

S. Voinigescu, R. Aroca, T. Dickson, S. Nicolson, T. Chalvatzis, P. Chevalier, P. Garcia, C. Gamier, B. Sautreuil
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引用次数: 20

Abstract

This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100degC. Inductor and transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described.
迈向2.5 v以下,100gb /s串行收发器
本文首先介绍了一种半速率、2.5 v、1.4 w、87gb /s的片上锁相环发射机,采用130纳米SiGe BiCMOS工艺生产。接下来,探讨了实现全速率100 gb /s串行收发器所需的最关键模块。最先进的105 ghz、SiGe HBT静态分频器和2.5 v电源下的压控振荡器,以及65纳米CMOS、1.2 v、90 ghz静态分频器、低相位噪声压控振荡器和100 ghz时钟分配网络放大器,在电源和工艺扩展以及高达100℃的温度下都具有充分的特点。还描述了纳米级CMOS和SiGe BiCMOS技术中电感器和变压器的建模和超过200 GHz的缩放。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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