Virtex-5 fpga电源优化的CAD技术

2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI:10.1109/CICC.2007.4405687

Subodh Gupta, J. Anderson, L. Farragher, Qiang Wang

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引用次数: 37

摘要

我们考虑了fpga的动态功耗，并提出了动态功耗降低的CAD技术。所提出的技术，包括功率感知放置，路由和新颖的后路由转换，用于优化在Xilinxreg Virtextrade-5 FPGA中实现的工业设计的功耗。一套工业设计的电路板级功率测量表明，这些技术平均可降低10%的功率。

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CAD Techniques for Power Optimization in Virtex-5 FPGAs

We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.

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2007 IEEE Custom Integrated Circuits Conference

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