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A W-band VCO using center-tapped basic inductor in 65nm CMOS 一种采用65nm CMOS中心抽头基本电感的w波段压控振荡器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864003
Jongsuk Lee, Yong Moon
{"title":"A W-band VCO using center-tapped basic inductor in 65nm CMOS","authors":"Jongsuk Lee, Yong Moon","doi":"10.1109/ISOCC.2013.6864003","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864003","url":null,"abstract":"A W-band voltage controlled oscillator (VCO) is implemented using 65nm CMOS process. The proposed VCO uses center-tapped inductor modified from basic structure and has high Q-factor. Inductor based LC type topology has many advantages compared with transmission line or waveguide. Also low cost CMOS process has many advantages than other processes. The designed VCO operates at 77.52~79.33GHz. The phase noise at 1MHz and 10MHz offset of 78GHz carrier are -81.6dBc/Hz and -102dBc/Hz respectively. Supply voltage is 0.9V and power consumption is 2.97mW. The chip area is 0.12×0.20mm2 and output power is -20.04dBm. Calculated FOM is -175.27dB.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115508115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A multicore approach to model-based analysis and design of Cyber-Physical Systems 基于模型的信息物理系统分析与设计的多核方法
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864027
A. Kanduri, A. Rahmani, P. Liljeberg, Kaiyu Wan, K. Man, J. Plosila
{"title":"A multicore approach to model-based analysis and design of Cyber-Physical Systems","authors":"A. Kanduri, A. Rahmani, P. Liljeberg, Kaiyu Wan, K. Man, J. Plosila","doi":"10.1109/ISOCC.2013.6864027","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864027","url":null,"abstract":"Embedded systems took a leap as combining computational elements with physical systems led to many novel applications, further saw the rise of a new domain - Cyber-Physical Systems (CPS). Growing importance for CPS in industry threw down many challenges in a designer's perspective ranging from computational methods, modeling platforms, programming structures, relevant hardware systems, etc. Ptolemy is the platform which is tailor made for such full scale design of networked and real time systems. In an effort to explore the suitability of Ptolemy II platform for CPS design, we chose an Unmanned Aerial vehicle (UAV) application as a case study. In this paper, we model UAV in Ptolemy II in a modular and hierarchical way such that the system meets the requirements of data flows and dependencies. Key parameters of a typical CPS such as schedulability and predictability were analyzed. In the end, to better the performance of UAV, computational tasks were mapped onto a networks-on-chip based multicore system. Our experimental results show the efficiency of our high level analysis and modeling and the extracted system requirements to enhance the system predictability.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124635463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reduced memory IFFT design for OFDM systems using DIT twiddle factor shifting algorithm 基于DIT抖动因子移位算法的OFDM系统减存IFFT设计
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864055
Ho-Yun Lee, Jun-Ho Kim, Jin-Gyun Chung
{"title":"Reduced memory IFFT design for OFDM systems using DIT twiddle factor shifting algorithm","authors":"Ho-Yun Lee, Jun-Ho Kim, Jin-Gyun Chung","doi":"10.1109/ISOCC.2013.6864055","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864055","url":null,"abstract":"In this paper, to reduce the memory size of IFFT for OFDM systems, we propose a new IFFT design based on a mapping of three IFFT input signals: modulated data, pilot and null signals. To reduce the memory cells, the proposed method focuses on reducing the size of memory cells in the bit-reversal part which requires the largest number of memory cells in IFFT. To this end, we propose a DIT(decimation-in-time) twiddle factor shifting algorithm to remove the multipliers in the first two stages. It is shown that the proposed method achieves a memory reduction of about 30% compared with conventional methods.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127279085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of hough transform feature extraction to reduce angular vibration in images captured from moving objects 应用霍夫变换特征提取降低运动物体图像的角振动
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864024
D. Afolabi, K. Man, Hai-Ning Liang, N. Zhang, E. Lim, Kaiyu Wan
{"title":"Application of hough transform feature extraction to reduce angular vibration in images captured from moving objects","authors":"D. Afolabi, K. Man, Hai-Ning Liang, N. Zhang, E. Lim, Kaiyu Wan","doi":"10.1109/ISOCC.2013.6864024","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864024","url":null,"abstract":"This paper details an ongoing research aimed at developing computational approach to reducing/eliminating vibration and light glare in images captured by digital cameras especially when the scene contains moving objects or the camera is mounted on a moving vehicle/flying drone. The algorithms developed are focused at real-time image acquisition where the enhanced/corrected images are need almost immediately after they are captured. The results show that these methods of reducing the stated problems are effective and it can be further developed for various applications.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"1938 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128968020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5-Gb/s 11.4mW half-rate CDR in 0.18μm CMOS 5gb /s 11.4mW半速率CDR, 0.18μm CMOS
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864042
Taek-Joon An, Jin-Ku Kang
{"title":"A 5-Gb/s 11.4mW half-rate CDR in 0.18μm CMOS","authors":"Taek-Joon An, Jin-Ku Kang","doi":"10.1109/ISOCC.2013.6864042","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864042","url":null,"abstract":"A low-power clock and data recovery(CDR) circuit with a phase detector(PD) using dynamic current-mode logic latches and a novel V/I converter is described. The proposed latch draws a current during half of the clock cycle and the proposed V/I converter includes the XOR function by itself. The half-rate CDR circuit is simulated using 5-Gb/s with 0.18-um CMOS technology, and the circuit consumes only 11.4mW from a 1.8-V supply.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power, highly linear, low noise amplifier (LNA) for Ultra-Wideband applications 低功耗，高线性，低噪声放大器(LNA)的超宽带应用
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/isocc.2013.6864046
Ayobami B. Iji
{"title":"Low power, highly linear, low noise amplifier (LNA) for Ultra-Wideband applications","authors":"Ayobami B. Iji","doi":"10.1109/isocc.2013.6864046","DOIUrl":"https://doi.org/10.1109/isocc.2013.6864046","url":null,"abstract":"One of the important components of a receiver is the low noise amplifier (LNA). The challenges of LNA design include ability to achieve high gain, low noise figure and better linearity at low power consumption within the required frequency. In this paper, our design is based on Impulse Response (IR) Ultra-Wideband (UWB) transceiver operating at 3.1-4.6GHz. Hence the LNA designed has been optimized for Low noise figure, considerably high gain and better linearity at low power consumption, which make it suitable for implant-able radio application. The process technology used here is 0.25μm CMOS Silanna process.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132696353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power GPS/Galileo/GLONASS receiver in 65nm CMOS 低功耗GPS/Galileo/GLONASS接收器，65nm CMOS
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864017
Huijung Kim, Jeong-Hyun Choi, Sang-Yun Lee, Taewan Kim, Jung-woo Kim, Jong-Dae Bae, Chaehag Yi, Hyunwon Moon
{"title":"A low power GPS/Galileo/GLONASS receiver in 65nm CMOS","authors":"Huijung Kim, Jeong-Hyun Choi, Sang-Yun Lee, Taewan Kim, Jung-woo Kim, Jong-Dae Bae, Chaehag Yi, Hyunwon Moon","doi":"10.1109/ISOCC.2013.6864017","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864017","url":null,"abstract":"A low power GPS/Galileo/GLONASS receiver is presented. The single chip supports GPS/Galileo and GLONASS operation simultaneously. To operate both application simultaneously, two mixers and two baseband filters are used. The chip size is 3.24 mm2 including bonding PAD. The system noise figure (NF) is 1.95 dB including SAW filter which loss is 1 dB. Power consumption is 23.6 mW for GPS/Galileo operation and 25.4 mW for GLONASS operation from 1.2V supply.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133762180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-speed radix-4 Add-Compare-Select unit for next generation communication systems 用于下一代通信系统的高速基数4添加比较选择单元
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863958
Wooseok Byun, Ji-Hoon Kim
{"title":"High-speed radix-4 Add-Compare-Select unit for next generation communication systems","authors":"Wooseok Byun, Ji-Hoon Kim","doi":"10.1109/ISOCC.2013.6863958","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863958","url":null,"abstract":"ACS (Add-Compare-Select) units are the most important block in FEC (Forward Error Correction) decoders such as Viterbi decoder and Turbo decoder. Due to the increase of performance requirement in next generation mobile communication systems such as LTE-Advanced, high speed operation of ACS units also becomes more important to achieve high throughput requirement. In this paper, we present three types of high-speed radix-4 ACS unit implementation for 12-bit operands and compare hardware complexities for various operating clock periods with 40% margin in 65nm CMOS process.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133901360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 60GHz power amplifier with 12.1 dBm & P1dBCP in 0.18um SiGe BiCMOS process 采用0.18um SiGe BiCMOS工艺，功率为12.1 dBm, P1dBCP的60GHz功率放大器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863955
W. M. Lim, J. Gu, Jialin Feng, K. Yeo, Xiaopeng Yu, L. Siek, K. M. Lim, C. Boon, Wanlan Yang, Jinna Yan
{"title":"A 60GHz power amplifier with 12.1 dBm & P1dBCP in 0.18um SiGe BiCMOS process","authors":"W. M. Lim, J. Gu, Jialin Feng, K. Yeo, Xiaopeng Yu, L. Siek, K. M. Lim, C. Boon, Wanlan Yang, Jinna Yan","doi":"10.1109/ISOCC.2013.6863955","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863955","url":null,"abstract":"This paper describes the design and analysis of a four-stages 60GHz SiGe BiCMOS power amplifier. The proposed circuit uses single-ended common-emitter topology that draws 72mW from 1.8V supply. It is able to deliver 12.1dBm output, 17.4dB power gain with a peak 14.1% PAE at its compression point. The S21 has a 3dB bandwidth from 55GHz to 67GHz, which covers the whole of 60GHz band. The power amplifier occupy a silicon area of 1.1 × 0.46 um2 and the measured results show that it can be fully adopted in the 60GHz ISM band applications.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134088371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 10b 50MS/s 90nm CMOS skinny-shape ADC using variable references for CIS applications 一个10b 50MS/s 90nm CMOS瘦形ADC使用可变参考的CIS应用
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863990
Jun-Sang Park, Tai-Ji An, Yongmin Kim, Suk-Hee Cho, Hyun-Sun Shim, Woo-Jin Jang, Yongsik Shin, Jun-Hyup Lee, G. Ahn, Seunghoon Lee
{"title":"A 10b 50MS/s 90nm CMOS skinny-shape ADC using variable references for CIS applications","authors":"Jun-Sang Park, Tai-Ji An, Yongmin Kim, Suk-Hee Cho, Hyun-Sun Shim, Woo-Jin Jang, Yongsik Shin, Jun-Hyup Lee, G. Ahn, Seunghoon Lee","doi":"10.1109/ISOCC.2013.6863990","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863990","url":null,"abstract":"This work proposes a skinny-shape 10b 50MS/s 90nm CMOS four-step pipeline ADC for various CIS applications. The proposed ADC converts analog signals in variable signal-swing ranges of 1.12 to 1.60Vp-p into low voltage-based digital data. The proposed on-chip I/V reference circuits generate the required variable reference voltages with a fixed common-mode level using a single external control voltage. The prototype ADC implemented in a 90nm CMOS process shows a maximum SNDR and SFDR of 55.1dB and 65.6dB, respectively. The ADC with an active die area of 0.23mm2 consumes 17.5mW at 50MS/s using dual supply voltages of 2.5V for analog and 1.2V for digital.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130320901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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