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2013 International SoC Design Conference (ISOCC)最新文献

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A two-point tuning LC VCO with minimum variation of KVCO2 for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS 用于65纳米CMOS四波段GSM/GPRS/EDGE极性发射机的最小KVCO2变化两点调谐LC压控振荡器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864004
Taemin Kim, Jihoon Son, Hae-jin Kim, Hyunchol Shin
{"title":"A two-point tuning LC VCO with minimum variation of KVCO2 for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS","authors":"Taemin Kim, Jihoon Son, Hae-jin Kim, Hyunchol Shin","doi":"10.1109/ISOCC.2013.6864004","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864004","url":null,"abstract":"A two-point tuning VCO with switchable secondary tuning gain KVCO2 is designed in 65nm CMOS for a two-point modulation PLL-based phase modulator that is to serve as phase-modulating part of a quad-band GSM/GPRS/EDGE polar transmitter. The two-point tuning VCO employs two varactor banks for dual tuning capability. The second varactor bank is a differentially tuned structure and its gain KVCO2 is switchable to minimize its variation for maintaining optimum second-point modulation gain. Fabricated in 65nm CMOS, the VCO draws 8 mA from 2 V supply. It covers the 2930-4150 MHz. The phase noise is -142dBc/Hz at 10MHz offset for 3.9 GHz output frequency. The silicon area of the VCO and accompanying dividers is 810 × 600 μm2.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"7 s2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132360543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and evaluation of a voltage-mode/current-mode hybrid logic circuit for a low-power fine-grain reconfigurable VLSI 用于低功耗细粒度可重构VLSI的电压模式/电流模式混合逻辑电路的设计与评估
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864057
Xu Bai, M. Kameyama
{"title":"Design and evaluation of a voltage-mode/current-mode hybrid logic circuit for a low-power fine-grain reconfigurable VLSI","authors":"Xu Bai, M. Kameyama","doi":"10.1109/ISOCC.2013.6864057","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864057","url":null,"abstract":"This paper proposes a low-power two-variable logic circuit based on mixed voltage-mode/current-mode logic design. The voltage- and current-mode operations can be selected for low power consumption at low and high frequency, respectively, according to speed requirement. An nMOS pass transistor network is shared to realize voltage switching and current steering for the voltage- and current-mode operations, respectively, which leads to high utilization of the hardware resources. As a result, the power consumption of the hybrid two-variable logic circuit is lower than that of the conventional two-input look-up table (LUT) using CMOS transmission gates, when the operating frequency is more than 800 MHz. The delay and area of the hybrid two-variable logic circuit are increased by only 7% and 13%, respectively.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128348599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 50-MHz clock generator with voltage and temperature compensation using low dropout regulator 50mhz时钟发生器，电压和温度补偿采用低差调节器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863996
Chua-Chin Wang, Tzu-Chiao Sung, Tzu-Yi Yang, Yi-Jie Hsieh
{"title":"A 50-MHz clock generator with voltage and temperature compensation using low dropout regulator","authors":"Chua-Chin Wang, Tzu-Chiao Sung, Tzu-Yi Yang, Yi-Jie Hsieh","doi":"10.1109/ISOCC.2013.6863996","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863996","url":null,"abstract":"This paper presents a clock generator featuring a feedback temperature and voltage compensation circuit and low dropout regulator circuit on-chip capable of constraining frequency variation to 3.49 %. The inclusion of an OPA, MOS transistors and resistors eliminates the need of large BJT devices to reduce the area penalty and achieve low power consumption. Particularly, a negative feedback temperature compensation bias circuit utilizes only a MOS transistor and a resistor to improve compensation capability. The proposed design is implemented using TSMC 0.18 μm CMOS process followed by simulation in the temperature range between of 0 oC to 100 oC. The post-layout-extracted simulation results reveal that the worst-case error is less than 2 mV with calibration, which is 72 % improvement compared with the state of art.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"591 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133073975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transistor layout optimization for leakage saving 晶体管布局优化以节省漏电
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864020
Myunghwan Ryu, Yesung Kang, Youngmin Kim
{"title":"Transistor layout optimization for leakage saving","authors":"Myunghwan Ryu, Yesung Kang, Youngmin Kim","doi":"10.1109/ISOCC.2013.6864020","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864020","url":null,"abstract":"In this paper, we investigate electrical effects of transistor layout shape (both in the channel and diffusion) on the performance and leakage current. Through layout optimization techniques, we propose a novel intra-gate biasing technique to reduce leakage current while maintaining drive current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. Diffusion rounding is another interesting effect which happens due to the imperfect source and drain profile in the sub-wavelength lithography regime. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased Ion with decreased Ioff because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement both in the on-current (driving) and the off-current (leakage).","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133343631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel high throughput high resolution two-stage oscillator-based TDC 一种基于两级振荡器的新型高通量高分辨率TDC
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864043
M. Abdelmejeed, R. Guindi, M. Abdel-Moneum
{"title":"A novel high throughput high resolution two-stage oscillator-based TDC","authors":"M. Abdelmejeed, R. Guindi, M. Abdel-Moneum","doi":"10.1109/ISOCC.2013.6864043","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864043","url":null,"abstract":"This paper presents a new technique to reduce the conversion time, hence improve the throughput, of the two-stage Time to Digital Converter (TDC) architecture. An oscillator based TDC is used in the first and second stages. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of phase-shift between two oscillating signals. A throughput of 400 MS/s, a DNL of 0.38, and an INL of 0.36 are achieved.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121967401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A fully integrated UHF passive tag IC having one-time programmable memory in standard CMOS technology 一个完全集成的超高频无源标签IC，在标准CMOS技术中具有一次性可编程存储器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863957
Vinh-Hao Duong, N. Phan, Hyun-Sik Lee, Dasom Park, Jong-Wook Lee
{"title":"A fully integrated UHF passive tag IC having one-time programmable memory in standard CMOS technology","authors":"Vinh-Hao Duong, N. Phan, Hyun-Sik Lee, Dasom Park, Jong-Wook Lee","doi":"10.1109/ISOCC.2013.6863957","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863957","url":null,"abstract":"We present a 2-Kb one-time programmable (OTP) memory for high security RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 μm 1-poly 6-metal standard CMOS process with no additional masks.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131600705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design for low current mismatch in the CMOS charge pump CMOS电荷泵的低电流失配设计
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864035
M. Shiau, Ching-Hwa Cheng, Heng-Shou Hsu, Hong-Chong Wu, H. Weng, J. Hou, R. Sun, Kai-Che Liu, Guang-Bao Lu, Don-Gey Liu
{"title":"Design for low current mismatch in the CMOS charge pump","authors":"M. Shiau, Ching-Hwa Cheng, Heng-Shou Hsu, Hong-Chong Wu, H. Weng, J. Hou, R. Sun, Kai-Che Liu, Guang-Bao Lu, Don-Gey Liu","doi":"10.1109/ISOCC.2013.6864035","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864035","url":null,"abstract":"In this study, the charge pump (CP) was designed by gain-boosting amplifiers for lower mismatching. In this design two differential amplifiers were employed to reduce the effect of the channel length modulation in the transistors. This circuit was implemented by the 0.18-μm CMOS technology of TSMC at a power supply of 1.8 V. In our study, the measured mismatch was less than 1% for the output from 0.4 to 1.4 V which is very good for PLL applications.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130554184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Overview of design techniques for energy efficiency improvement in advanced CMOS technology 在先进的CMOS技术中提高能源效率的设计技术概述
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864022
T. T. Kim
{"title":"Overview of design techniques for energy efficiency improvement in advanced CMOS technology","authors":"T. T. Kim","doi":"10.1109/ISOCC.2013.6864022","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864022","url":null,"abstract":"The ever more increasing interest and requirement on energy efficient circuits and systems have demanded design techniques from various angles. While supply voltage scaling has been widely accepted as a solution for energy efficiency improvement, the energy efficiency improvement from supply scaling is limited. Therefore, all the design challenges caused by the voltage scaling have to be tackled at all abstraction levels. In this paper, an overview of various state-of-the-art design techniques for energy efficiency improvement is presented.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of early stopping unit in parallel turbo decoder based on galois field operation 基于伽罗瓦现场运行的并联式涡轮解码器早期停止单元设计
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863983
Hyeji Kim, Ji-Hoon Kim
{"title":"Design of early stopping unit in parallel turbo decoder based on galois field operation","authors":"Hyeji Kim, Ji-Hoon Kim","doi":"10.1109/ISOCC.2013.6863983","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863983","url":null,"abstract":"The early stopping of turbo decoder is widely used in LTE/LTE-Advanced systems to avoid unnecessary iterations. To achieve high throughput requirements in next generation mobile communication systems, parallel turbo decoding where multiple SISO (Soft-Input Soft-Output) decoders work is commonly employed. Although CRC (Cyclic Redundancy Check)-based stopping criterion is well known by its superior performance, conventional CRC implementation is hard to be applied to parallel turbo decoding due to the timing overhead incurred by the intrinsic feature where the input data should be serialized. In this paper, to reduce the timing overhead, we present the parallel CRC architecture based on GF (Galois field) operations with negligible hardware overhead.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"413 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124421040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 6-bit 500MS/s CMOS A/D converter with a digital input range detection circuit 一个带有数字输入距离检测电路的6位500MS/s CMOS A/D转换器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864037
Dai Shi, Gi-Yoon Lee, Sang Min Lee, K. Yoon
{"title":"A 6-bit 500MS/s CMOS A/D converter with a digital input range detection circuit","authors":"Dai Shi, Gi-Yoon Lee, Sang Min Lee, K. Yoon","doi":"10.1109/ISOCC.2013.6864037","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864037","url":null,"abstract":"A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124432980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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