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2013 International SoC Design Conference (ISOCC)最新文献

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A CEA concentration measurement system using FPW biosensors and frequency-shift readout IC 采用FPW生物传感器和频移读出集成电路的CEA浓度测量系统
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863977
Chua-Chin Wang, Tzu-Chiao Sung, Chiang-Hsiang Liao, Chia-Ming Chang, Je-Wei Lan, I. Huang
{"title":"A CEA concentration measurement system using FPW biosensors and frequency-shift readout IC","authors":"Chua-Chin Wang, Tzu-Chiao Sung, Chiang-Hsiang Liao, Chia-Ming Chang, Je-Wei Lan, I. Huang","doi":"10.1109/ISOCC.2013.6863977","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863977","url":null,"abstract":"In this paper, a CEA (carcinoembryonic antigen) concentration measurement system using flexural plate wave (FPW) biosensors and a frequency-shift readout IC is presented. The proposed frequency-shift readout method employs a programmable frequency generator and a peak detecting scheme to estimate the resonant frequency. The programmable frequency generator provides a frequency scanning range from 0.9 MHz to 25 MHz according to the characteristics of the FPW biosensors. Particularly, the proposed frequency-shift readout circuit filters and amplifies the FPW biosensors signals such that the requirements for the following voltage peak detector can be relaxed. Therefore, the sensitivity and performance of the CEA sensing system are also enhanced. The sensitivity of the peak detector is 5 mV at the highest signal rate, 50 MHz. The proposed frequency-shift readout circuit is implemented using a typical 0.18 μm CMOS technology. The power consumption of the proposed CEA concentration measurement system is 7.69 mW justified by HSPICE simulations.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies 采用传统硅技术和新型碳纳米管晶体管技术的高频 32 位动态加法器比较
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863980
Yanan Sun, V. Kursun
{"title":"A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies","authors":"Yanan Sun, V. Kursun","doi":"10.1109/ISOCC.2013.6863980","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863980","url":null,"abstract":"The performances of high-frequency two-stage pipeline 32-bit carry lookahead adders are evaluated in this paper with the following three different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, and carbon nanotube MOSFET (CN-MOSFET) NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53% and 77.96% as compared to the conventional Si-MOSFET domino and Si-MOSFET NP dynamic CMOS adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54% and 95.57% as compared to the Si-MOSFET domino and Si-MOSFET NP dynamic CMOS circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the silicon circuits that are evaluated in this study.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"49 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120845184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Source follower based single ended sense amplifier for large capacity SRAM 基于源从动器的大容量SRAM单端检测放大器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864051
Dong-Hoon Jung, Hanwool Jeong, T. Song, Gyuhong Kim, Seong-ook Jung
{"title":"Source follower based single ended sense amplifier for large capacity SRAM","authors":"Dong-Hoon Jung, Hanwool Jeong, T. Song, Gyuhong Kim, Seong-ook Jung","doi":"10.1109/ISOCC.2013.6864051","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864051","url":null,"abstract":"In this paper we proposed a source follower based single ended sense amplifier (SA) which enhance the access time using positive feedback. The source follower stage is used to transfer the bit-line (BL) development to sensing stage. By using the source follower, biasing of the sensing circuit during the precharge phase becomes faster. In addition, positive feedback is applied to the source follower stage to enhance the access time of the SRAM macro with the large number of cells per bit-line (CpBL). The proposed source follower based SA is designed and verified using 45nm CMOS process. More than to 12% of access time enhancement is achieved compared to conventional structures.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125077141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low jitter spread spectrum clock generator using varactor delay line 采用变容延迟线的低抖动扩频时钟发生器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864047
G. Singh
{"title":"A low jitter spread spectrum clock generator using varactor delay line","authors":"G. Singh","doi":"10.1109/ISOCC.2013.6864047","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864047","url":null,"abstract":"A spread spectrum clock generator (SSCG) is realized using varactor based delay line and a dejittering PLL. This varactor based delay line utilizes the delay-modulation to phase-modulation property to generate an intermediate spread-spectrum input clock. This SSCG has been fabricated in a 0.18μm double-poly six metal CMOS process and it consumes 35mW from the supply of 1.8V. The proposed SSCG can generate clocks 27MHz, 54MHz and 108MHz with centre-spread ratios of +/-0.25%. The measured peak-to-peak cycle-to-cycle jitter is less than 100ps and the measured electromagnetic interference reduction amount is 2.8dB.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"36 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116111072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An H.265/HEVC codec for UHD(3840×2160) capturing and playback 用于UHD(3840×2160)捕获和播放的H.265/HEVC编解码器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864013
Jae-Sung Yoon, Choonseung Lee, Changsoo Park, Gang-Hyeon Lee, K. Lee, Sungho Roh, Minsu Jeon, Youngbeom Jung, Jinhong Oh, Jin-Aeon Lee
{"title":"An H.265/HEVC codec for UHD(3840×2160) capturing and playback","authors":"Jae-Sung Yoon, Choonseung Lee, Changsoo Park, Gang-Hyeon Lee, K. Lee, Sungho Roh, Minsu Jeon, Youngbeom Jung, Jinhong Oh, Jin-Aeon Lee","doi":"10.1109/ISOCC.2013.6864013","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864013","url":null,"abstract":"An H.265/HEVC codec(encoder/decoder) for UHD(3840×2160) capturing and playback is presented. Implemented codec has 0.97 mm2 logic area in 20nm with 170KB internal memory. By exploiting sophisticated low-power design, 56/190 mW power consumption is achieved in UHD 30fps decoding/encoding. Maintaining UHD 30fps real-time encoding, the encoder allows about 1.0 dB quality drop compared to HM reference model. By introducing pixel cache for reference pixel read for motion estimation/compensation, the codec consumes 1.2 / 2.0 GB/s external memory bandwidth at UHD 30fps decoding/encoding.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121169913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel folded active inductor for wireless communication SoC 一种用于无线通信SoC的新型折叠有源电感
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864034
Y. Lai, C. Zheng
{"title":"A novel folded active inductor for wireless communication SoC","authors":"Y. Lai, C. Zheng","doi":"10.1109/ISOCC.2013.6864034","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864034","url":null,"abstract":"A gyrator-based active inductor with a folded circuit structure for wireless communication system-on-a-chip (SoC) applications is proposed herein. The metal-oxide-semiconductor field-effect transistors (MOSFETs) comprise a gyrator and a capacitor, which generate inductive property. The gyrator-based active inductor is thereby created. The negative-resistance compensation technology is utilized to compensate for the losses produced by the transistors and the bias circuitry. Inductance values from 0.02 to 82.20 nH are exhibited. Characteristics of high quality factor and wide inductance range are achieved by the folded active inductor.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127777334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sensing circuit optimization using different type of transistors for deep submicron STT-RAM 基于不同类型晶体管的深亚微米STT-RAM传感电路优化
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863987
Byungkyu Song, T. Na, Jisu Kim, Seung H. Kang, Jung Pill Kim, Seong-ook Jung
{"title":"Sensing circuit optimization using different type of transistors for deep submicron STT-RAM","authors":"Byungkyu Song, T. Na, Jisu Kim, Seung H. Kang, Jung Pill Kim, Seong-ook Jung","doi":"10.1109/ISOCC.2013.6863987","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863987","url":null,"abstract":"In this paper, we propose an optimal combination of transistor types in the conventional sensing circuit. A sensing margin, which determines the read yield of STT-RAM, is sensitive to the Vth type of several transistors in the sensing circuit. Thus, the optimization of the sensing circuit using different types of transistors is important for designing the sensing circuit in STT-RAM. Using industry compatible 45-nm model parameters, Monte Carlo HSPICE simulation results show that the conventional sensing circuit optimized using different types of transistors achieves read access pass yield enhancement of 10% when compared to the conventional sensing circuit using typical transistors.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133943180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Verilog synthesis of USB 2.0 full-speed device PHY IP Verilog合成USB 2.0全速设备PHY IP
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863961
Kee-Bum Shin, Kihwan Seong, Dong-Hee Yeo, Byungsub Kim, J. Sim, Hong-June Park
{"title":"Verilog synthesis of USB 2.0 full-speed device PHY IP","authors":"Kee-Bum Shin, Kihwan Seong, Dong-Hee Yeo, Byungsub Kim, J. Sim, Hong-June Park","doi":"10.1109/ISOCC.2013.6863961","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863961","url":null,"abstract":"A full-speed USB 2.0 device PHY IP chip is implemented in FPGA by using a Verilog synthesis. It works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX. The TX and RX circuits include a NRZI encoder/decoder, a bit stuffer/unstuffer and a serializer/deserializer. The clock generator accepts a 60MHz clock and generates five 12MHz clock signals which are spaced uniformly in time and synchronized to the 60MHz clock. The five 12MHz clocks are enable signals of TX and RX circuits. The 60MHz clock is used as the clock signal of the TX and RX circuits. The 60MHz clock are used for blind oversampling of CDR. An external 1.5kohm resistor is connected between the D+ node and VDD to notify the connection of the device PHY to the host PC.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127578424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fast synchronization algorithm for the Forward Error Correction in IEEE Standard 802.3 IEEE 802.3标准中前向纠错的快速同步算法
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864030
Yang Liu, Chengwei Song, Yufei Li
{"title":"Fast synchronization algorithm for the Forward Error Correction in IEEE Standard 802.3","authors":"Yang Liu, Chengwei Song, Yufei Li","doi":"10.1109/ISOCC.2013.6864030","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864030","url":null,"abstract":"A shortened cyclic code (known as Forward Error Correction [FEC]) aimed at increasing link budget and Bit Error Rate (BER) performance is introduced in section 74 of IEEE Standard 802.3. FEC is widely used in High Speed Serdes communication applications like 10G/40G Ethernet. This paper proposes a synchronize algorithm for chip implementation which quickly detect the boundary of the received code block. Compared with the algorithm outlined in the 802.3 standard, the proposed one improves synchronization time by three orders of magnitude.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129383153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient TSV repair method for 3D memories 三维存储器的高效TSV修复方法
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863974
Ilwoong Kim, Keewon Cho, Sungho Kang
{"title":"Efficient TSV repair method for 3D memories","authors":"Ilwoong Kim, Keewon Cho, Sungho Kang","doi":"10.1109/ISOCC.2013.6863974","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863974","url":null,"abstract":"Through-silicon-via (TSV) based 3D stacked memory is recognized as the next generation memory architecture but its low TSV yield is one of the manufacturing cost factors. In this paper, an efficient TSV repair method is proposed for 3D memories. The proposed method uses a new 2-dimensional 1-4 switching technique to enable efficient repair of clustered TSV faults using repair circuitry with reasonable area overhead. Therefore, the proposed TSV repair method can contribute the improvement of TSV yield for 3D memories.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133253431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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