Verilog synthesis of USB 2.0 full-speed device PHY IP

A full-speed USB 2.0 device PHY IP chip is implemented in FPGA by using a Verilog synthesis. It works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX. The TX and RX circuits include a NRZI encoder/decoder, a bit stuffer/unstuffer and a serializer/deserializer. The clock generator accepts a 60MHz clock and generates five 12MHz clock signals which are spaced uniformly in time and synchronized to the 60MHz clock. The five 12MHz clocks are enable signals of TX and RX circuits. The 60MHz clock is used as the clock signal of the TX and RX circuits. The 60MHz clock are used for blind oversampling of CDR. An external 1.5kohm resistor is connected between the D+ node and VDD to notify the connection of the device PHY to the host PC.