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Design of 20-GHz low noise amplifier for automotive collision avoidance application 汽车防撞用20 ghz低噪声放大器的设计
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864001
Akilan Thangarajah, H. Hsu, M. Ekpanyapong, C. Punyasai, Yi-Te Chou, Nai-Chen Liu
{"title":"Design of 20-GHz low noise amplifier for automotive collision avoidance application","authors":"Akilan Thangarajah, H. Hsu, M. Ekpanyapong, C. Punyasai, Yi-Te Chou, Nai-Chen Liu","doi":"10.1109/ISOCC.2013.6864001","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864001","url":null,"abstract":"Low-noise amplifier (LNA) is a very critical component in terms of its functionality in a transceiver. This paper presents design of a 20-GHz low-noise amplifier in TSMC 0.18μm technology. The design utilizes multi-stage topology which includes three transistors. First-stage is a single ended common-source topology while the second stage is current reused topology. Post layout simulations show that the proposed LNA exhibits gain of 14.7dB, noise figure of 3.4dB while it consumes only 10.62mW. Moreover, the chip area of the LNA is 0.5175mm2.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114576469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The hysteretic buck converter with thermister 带热敏电阻的滞回降压变换器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863991
Donghun Lee, Taejin Jung, Woo-Seong Kang, Kiyoon Lee, Su-hun Yang, Ji-hyun Park, Ji-San Choi, Kwangsub Yoon
{"title":"The hysteretic buck converter with thermister","authors":"Donghun Lee, Taejin Jung, Woo-Seong Kang, Kiyoon Lee, Su-hun Yang, Ji-hyun Park, Ji-San Choi, Kwangsub Yoon","doi":"10.1109/ISOCC.2013.6863991","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863991","url":null,"abstract":"This paper proposes the hysteretic buck converter with thermister to minimize the output ripple votage. The conventional hysteretic buck converter shows fast response, but it suffers from the large ripple voltage due to the logic switching. The proposed hysteretic buck converter employs the switched-capacitor techniques with comparators to maintain the minimum ripple voltage. The simulation results demonstrate that the proposed circuit was able to reduce the output ripple voltage more than 20% with respect to the conventional ones.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117268874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scan chain swapping using TSVs for test power reduction in 3D-IC 使用tsv进行扫描链交换以测试3D-IC中的功耗降低
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863963
Ingeol Lee, Jaeseok Park, Sungho Kang
{"title":"Scan chain swapping using TSVs for test power reduction in 3D-IC","authors":"Ingeol Lee, Jaeseok Park, Sungho Kang","doi":"10.1109/ISOCC.2013.6863963","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863963","url":null,"abstract":"Although the hot issue of chip design becomes 3-dimensional IC, design for testability is still mandatory part of chip design. Scan structure is widely used for system reliability. However, power consumption and heat problems are necessarily considered when design is under test. In this paper, scan chain swapping method using TSVs is presented to reduce shift power in scan in operation. Proper X-filling and swapping algorithm can improve proposed scan chain swapping method. The experiment result demonstrates the power reduction in test mode.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124930136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The design of bus accessing timing to NAND flash array for high bandwidth 高带宽NAND闪存阵列总线访问时序设计
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864026
Cheng Li-xin, Yue Yang, Liu Yun-yun, J. Seon, K. Man
{"title":"The design of bus accessing timing to NAND flash array for high bandwidth","authors":"Cheng Li-xin, Yue Yang, Liu Yun-yun, J. Seon, K. Man","doi":"10.1109/ISOCC.2013.6864026","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864026","url":null,"abstract":"To improve the reading and writing speed of NAND flash array with multi-channel and multi-way, and to obtain the highest available bandwidth, an approach is presented in this paper. One mechanism of high efficiency bus accessing timing scheme based on interleaving is introduced into the approach. In pursuance of this timing, flash controllers are able to make every plane in the flash array to be active in parallel. Therefore the transmission ability to and from the bus can be greatly improved. Utilizing this approach, the accessing efficiency to the NAND flash array will be pushed to a very high level. According to the testing results, as opposed to normal flash bus timing scheme, the data reading efficiency can be increased by 68.5%, and the data writing efficiency can be increased by 457%, with the flash bus timing scheme presented in this paper being used. The conclusion can be drawn that the flash bus timing scheme presented in this paper is effective, and the reading and writing at very high speed to the NAND flash array can be realized.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125131474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive routing in MPSoCs using an efficient path-based method 基于有效路径的mpsoc自适应路由
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863978
Poona Bahrebar, D. Stroobandt
{"title":"Adaptive routing in MPSoCs using an efficient path-based method","authors":"Poona Bahrebar, D. Stroobandt","doi":"10.1109/ISOCC.2013.6863978","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863978","url":null,"abstract":"On-chip communication appears to have an extremely significant role in taking advantage of the inherent parallelization offered by the MPSoCs. If interconnection networks are to be used efficiently in such platforms, designing high-performance routing algorithms is inevitable. In this paper, a deadlock-free and highly adaptive multicast/unicast routing method is presented based on the Hamiltonian routing model. This method strives for a high degree of adaptiveness by finding the maximum number of minimal paths between each pair of source and destination. Experimental results demonstrate that the proposed method significantly outperforms the other adaptive and non-adaptive algorithms in terms of latency and power consumption. This efficiency is achieved by alleviating the number of hotspots through a better traffic distribution all over the network.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129443193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.8-V 4.36-ppm/°C-TC bandgap reference with temperature variation calibration 一个1.8 v 4.36 ppm/°C-TC带隙参考温度变化校准
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863997
Wei-Bin Yang, Horng-Yuan Shih, Yu-Yao Lin, M. Hong, Chi-Hsiung Wang, Y. Lo
{"title":"A 1.8-V 4.36-ppm/°C-TC bandgap reference with temperature variation calibration","authors":"Wei-Bin Yang, Horng-Yuan Shih, Yu-Yao Lin, M. Hong, Chi-Hsiung Wang, Y. Lo","doi":"10.1109/ISOCC.2013.6863997","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863997","url":null,"abstract":"A bandgap reference generator with a compensation circuit against temperature variation is presented. The bandgap reference generator provides a reference current of 10μA with temperature coefficient (TC) of only 4.36ppm/°C under temperature range from -40 to 125°C. The chip is fabricated in a 0.18-μm standard CMOS process with a 1.8V power supply voltage, and the active die area is 0.008mm2.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115866471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra-low-power robust and compatible digital IPs for passive RF devices 用于无源射频器件的超低功耗、鲁棒性和兼容数字ip
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6863956
Weiwei Shi, C. Choy
{"title":"Ultra-low-power robust and compatible digital IPs for passive RF devices","authors":"Weiwei Shi, C. Choy","doi":"10.1109/ISOCC.2013.6863956","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6863956","url":null,"abstract":"Robust digital part IP designs for passive RF components are presented in this paper. For the consideration of low power and subthreshold supply, energy-aware structure with mixed counter and pre-counted addition are applied for the circuit design. Tailored structures help to reduce the impact of frequency variation and simplify other block design in the tag. Fabricated in different deep submicron CMOS technologies, the design chips show enough robustness in measurement with variable power supply and wide-range clock frequency. They consume ultra-low power with high compatibility and stability.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127262044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
28nm high-K metal gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor 28nm高k金属栅极异构四核cpu，用于高性能节能移动应用处理器
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864006
Youngmin Shin, Hoi-Jin Lee, K. Shin, Prashant Kenkae, R. Kashyap, Dongjoo Seo, B. Millar, Yohan Kwon, Ravi Iyengar, Min-su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Sung Ho Park
{"title":"28nm high-K metal gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor","authors":"Youngmin Shin, Hoi-Jin Lee, K. Shin, Prashant Kenkae, R. Kashyap, Dongjoo Seo, B. Millar, Yohan Kwon, Ravi Iyengar, Min-su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Sung Ho Park","doi":"10.1109/ISOCC.2013.6864006","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864006","url":null,"abstract":"This paper presents a heterogeneous configuration of two different target quad-core CPUs. To support both high-performance and high energy-efficiency depending on application requirements, two types of quad-core CPUs are implemented in one mobile application processor. The first type quad-core CPU is designed to give the highest performance at the cost of reasonable power consumption. The second type quad-core CPU is optimized with emphasis on energy efficiency than high performance. This paper addresses the design features for high-performance quad-core CPU and the design optimization issue for low-power quad-core CPU. The best performance shows 1.8X of performance at the lowest power. The lowest power is reduced to 1/5 of power at the highest performance. Our heterogeneous configuration of separate implementations can be a more efficient solution for different power and performance requirements of various mobile applications.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127956105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
USB power saving techniques by partial power management USB省电技术通过部分电源管理
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864007
Yang SeungSoo, Byun HoJun
{"title":"USB power saving techniques by partial power management","authors":"Yang SeungSoo, Byun HoJun","doi":"10.1109/ISOCC.2013.6864007","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864007","url":null,"abstract":"This paper suggests a new USB runtime partial power management(PM) technique when USB connection is established, active. The USB specification has no PM during the active time but this new USB partial PM adds USB bus activity aware methods to reduce power consumption with partial gating and scaling of power and clock for USB H/W IPs. These methods could be applied to USB host mode and USB device mode.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127305194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of rectifier with comparator using unbalanced body biasing for wireless power transfer 采用不平衡体偏置的带比较器整流器的无线输电设计
2013 International SoC Design Conference (ISOCC) Pub Date : 2013-11-01 DOI: 10.1109/ISOCC.2013.6864049
Byeong Wan Ha, C. Cho
{"title":"Design of rectifier with comparator using unbalanced body biasing for wireless power transfer","authors":"Byeong Wan Ha, C. Cho","doi":"10.1109/ISOCC.2013.6864049","DOIUrl":"https://doi.org/10.1109/ISOCC.2013.6864049","url":null,"abstract":"This paper presents a rectifier with comparator using unbalanced body biasing for wireless power transfer in 0.11μm RF CMOS process. The proposed rectifier is composed of MOSFETs and two comparators. The comparator is used to reduce reverse leakage current occurring when the load DC voltage is higher than input RF voltage. For this purpose, unbalanced body biasing is devised. 0.837V sinusoidal RF input is rectified to 0.755V DC voltage, leading to 90% voltage conversion efficiency (VCE) at maximum. 13.56 MHz signal is used for input, and this circuit works up to 150 MHz signal keeping above 80% VCE.","PeriodicalId":129447,"journal":{"name":"2013 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130765104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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