发布求助
文献互助 智能选刊 最新文献

Symposium 1993 on VLSI Circuits最新文献

筛选
英文 中文
A 1 mW delta-sigma modulator for multichannel applications 用于多通道应用的1mw delta-sigma调制器
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920570
S. Sadeem, C. Sodini, H. Lee
{"title":"A 1 mW delta-sigma modulator for multichannel applications","authors":"S. Sadeem, C. Sodini, H. Lee","doi":"10.1109/VLSIC.1993.920570","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920570","url":null,"abstract":"A new oversampled A/D design methodology is proposed to significantly cut the power and area budget per channel of an oversampled analog-to-digital converter. The design and implementation of this low power and area, efficient delta-sigma modulator, which is the crucial building block for a multichannel system, is presented.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115860749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low power self refresh mode DRAM with temperature detecting circuit 具有温度检测电路的低功耗自刷新模式DRAM
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920531
Y. Kagenishi, H. Hirano, A. Shibayama, H. Kotani, N. Moriwaki, M. Kojima, T. Sumi
{"title":"Low power self refresh mode DRAM with temperature detecting circuit","authors":"Y. Kagenishi, H. Hirano, A. Shibayama, H. Kotani, N. Moriwaki, M. Kojima, T. Sumi","doi":"10.1109/VLSIC.1993.920531","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920531","url":null,"abstract":"To reduce self refresh mode current, a temperature detecting circuit, back bias generator and voltage down convertor, are developed. Using these circuits in a 16M DRAM, 33 /spl mu/A consuming current in self refresh mode has been realized at Vcc=5V, Ta=25 /spl deg/C.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123486263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 12 bit 600 kS/s digitally self-calibrated pipeline algorithmic ADC 一个12位600 k /s数字自校准流水线算法ADC
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920571
Hae-Seung Lee
{"title":"A 12 bit 600 kS/s digitally self-calibrated pipeline algorithmic ADC","authors":"Hae-Seung Lee","doi":"10.1109/VLSIC.1993.920571","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920571","url":null,"abstract":"This paper describes an algorithmic A/D converter which employs digital error correction and self-calibration. In this paper, an approach is described that employs a nominal radix 2, 1.5 bit/stage conversion algorithm. The technique discussed in this paper can be applied to any cyclic or pipelined algorithmic converter, does not require extra clock cycles during the conversion, and no additional analog circuitry is needed. The analog circuit is extremely simple, using one operational amplifier and two latches per stage.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124017872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture 采用三级流水线架构的250兆字节/秒同步DRAM
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920536
Y. Takai, M. Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Y. Fukuzo, H. Watanabe
{"title":"250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture","authors":"Y. Takai, M. Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Y. Fukuzo, H. Watanabe","doi":"10.1109/VLSIC.1993.920536","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920536","url":null,"abstract":"A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129520710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Capacitor-coupled complementary emitter-follower for ultra-high-speed low-power bipolar logic circuits 超高速低功耗双极逻辑电路的电容耦合互补发射-从动器
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920522
Y. Idei, N. Homma, T. Onai, K. Washio, T. Nishida, H. Nambu, K. Kanetani
{"title":"Capacitor-coupled complementary emitter-follower for ultra-high-speed low-power bipolar logic circuits","authors":"Y. Idei, N. Homma, T. Onai, K. Washio, T. Nishida, H. Nambu, K. Kanetani","doi":"10.1109/VLSIC.1993.920522","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920522","url":null,"abstract":"A complementary emitter follower composed of a direct-coupled npn transistor and a capacitor-coupled pnp transistor is proposed. Low power dissipation and good noise removing capability can be obtained by this coupling scheme. An ECL gate with this complementary emitter follower is 63% faster and has 4 times better load driving capability than a conventional ECL gate.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A well-synchronized sensing/equalizing method for sub-1.0 V operating advanced DRAMs 一种用于低于1.0 V工作的高级dram的良好同步传感/均衡方法
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920547
T. Ooishi, M. Asakura, S. Tomishima, H. Hidaka, K. Arimoto, K. Fujishima
{"title":"A well-synchronized sensing/equalizing method for sub-1.0 V operating advanced DRAMs","authors":"T. Ooishi, M. Asakura, S. Tomishima, H. Hidaka, K. Arimoto, K. Fujishima","doi":"10.1109/VLSIC.1993.920547","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920547","url":null,"abstract":"In standard DRAMs, a half-V/sub cc/ bit-line (BL) precharging method is widely used because of its several advantages. However this method faces several problems as the power supply voltage Vcc becomes lower. This paper describes such problems as the MOS transistors in the sensing/equalizing circuits are affected by the body effect, fluctuation of channel length (L), and leak current. It is thefefore difficult to decide the value of the V/sub th/ which satisfies the above conditions. Accordingly, we propose a well-synchronized sensing/equalizing method that enables an ultra low-voltage operation and makes determining the V/sub th/ easy.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131164753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 11O MHz/1 Mbit synchronous Tag RAM 一个110mhz / 1mbit同步标签RAM
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920517
Y. Unekawa, T. Kobayashi, T. Shirotori, Y. Fujimoto, T. Shimazawa, K. Nogami, T. Nakao, K. Sawada, M. Matsui, T. Sakurai, M. Tang, B. Huffman
{"title":"A 11O MHz/1 Mbit synchronous Tag RAM","authors":"Y. Unekawa, T. Kobayashi, T. Shirotori, Y. Fujimoto, T. Shimazawa, K. Nogami, T. Nakao, K. Sawada, M. Matsui, T. Sakurai, M. Tang, B. Huffman","doi":"10.1109/VLSIC.1993.920517","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920517","url":null,"abstract":"The synchronous Tag RAM reported in this paper holds addresses and status bits of cached data and can be used to build a secondary cache system of up to 16MBytes with external commodity synchronous SRAMs. In order to handle the large secondary cache, the present Tag RAM contains 1.189Mbit of 4T SRAM cells, the largest capacity ever reported for a Tag RAM. Short cycle time and small clock to D/sub OUT/ (data output) delay of the Tag RAM is crucial for a high-performance cache system. 9ns cycle operation and clock to D/sub OUT/ of 4.7ns in typical condition are achieved by a use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, a highly linear Voltage-Controlled Oscillator (VCO) for a Phase Locked Loop (PLL) and doubly placed self-timed write circuits. Since pure CMOS implementation cannot achieve the required speed, the device is manufactured with 0.7/spl mu/m double-polysilicon and double-metal BiCMOS technology.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Measurement of digital noise in mixed-signal integrated circuits 混合信号集成电路中数字噪声的测量
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920521
K. Makie-Fukuda, Takafumi Kikuchi, T. Matsuura, M. Hotta
{"title":"Measurement of digital noise in mixed-signal integrated circuits","authors":"K. Makie-Fukuda, Takafumi Kikuchi, T. Matsuura, M. Hotta","doi":"10.1109/VLSIC.1993.920521","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920521","url":null,"abstract":"A method of measuring digital noise in an analog circuit such as an A/D converter by a voltage comparator is proposed and the noise dependence was measured by a fabricated test chip. For mixed-signal ICs, it was shown that the effect of digital noise can be considerably reduced by using a differential configuration in analog circuits. The effect of digital noise can be further reduced by lowering the digital supply voltage. This can be achieved by lowering the supply voltage to the extent of the speed requirements of digital currents while keeping the analog supply voltage high enough to meet the required signal-to-noise ratio.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond 一种分布式的全局可替换的冗余方案，适用于半微米以下的ULSI存储器及其他存储器
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920561
T. Yamagata, Hirotoshi Sato, K. Fujita, Y. Nishimura, K. Anami
{"title":"A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond","authors":"T. Yamagata, Hirotoshi Sato, K. Fujita, Y. Nishimura, K. Anami","doi":"10.1109/VLSIC.1993.920561","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920561","url":null,"abstract":"A Distributed Globally Replaceable Redundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMs 待机/活动模式逻辑sub- 1v 1g / 4gb dram
Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI: 10.1109/VLSIC.1993.920548
D. Takashima, S. Watanabe, K. Sakui, H. Nakano, K. Ohuchi
{"title":"Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMs","authors":"D. Takashima, S. Watanabe, K. Sakui, H. Nakano, K. Ohuchi","doi":"10.1109/VLSIC.1993.920548","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920548","url":null,"abstract":"A new stand-by/active mode Logic I,II has been developed for the future 1G/4Gb DRAMs. The proposed Logic I, II can achieve sub-1V supply voltage operation with small l /spl mu/A subthreshold leakage current during stand-by cycle, by allowance of 1 mA transistor leakage current during the active cycle. The gate delay of Logic I is reduced by 37%-30% with the optimized channel widths for Vcc=O.8-1.5 V, as compared with that of the conventional logic. The gate delay of Logic II is also reduced by 85%-40% as compared with that of the conventional logic at Vcc=0.8-1.5 V. The proposed Logic I.II are easily applicable not only to 1G/4Gb DRAMs but also other types of memories such as SRAM and battery-operated memories.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122193951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信