Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMs

Abstract

A new stand-by/active mode Logic I,II has been developed for the future 1G/4Gb DRAMs. The proposed Logic I, II can achieve sub-1V supply voltage operation with small l /spl mu/A subthreshold leakage current during stand-by cycle, by allowance of 1 mA transistor leakage current during the active cycle. The gate delay of Logic I is reduced by 37%-30% with the optimized channel widths for Vcc=O.8-1.5 V, as compared with that of the conventional logic. The gate delay of Logic II is also reduced by 85%-40% as compared with that of the conventional logic at Vcc=0.8-1.5 V. The proposed Logic I.II are easily applicable not only to 1G/4Gb DRAMs but also other types of memories such as SRAM and battery-operated memories.