Y. Idei, N. Homma, T. Onai, K. Washio, T. Nishida, H. Nambu, K. Kanetani
{"title":"超高速低功耗双极逻辑电路的电容耦合互补发射-从动器","authors":"Y. Idei, N. Homma, T. Onai, K. Washio, T. Nishida, H. Nambu, K. Kanetani","doi":"10.1109/VLSIC.1993.920522","DOIUrl":null,"url":null,"abstract":"A complementary emitter follower composed of a direct-coupled npn transistor and a capacitor-coupled pnp transistor is proposed. Low power dissipation and good noise removing capability can be obtained by this coupling scheme. An ECL gate with this complementary emitter follower is 63% faster and has 4 times better load driving capability than a conventional ECL gate.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Capacitor-coupled complementary emitter-follower for ultra-high-speed low-power bipolar logic circuits\",\"authors\":\"Y. Idei, N. Homma, T. Onai, K. Washio, T. Nishida, H. Nambu, K. Kanetani\",\"doi\":\"10.1109/VLSIC.1993.920522\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A complementary emitter follower composed of a direct-coupled npn transistor and a capacitor-coupled pnp transistor is proposed. Low power dissipation and good noise removing capability can be obtained by this coupling scheme. An ECL gate with this complementary emitter follower is 63% faster and has 4 times better load driving capability than a conventional ECL gate.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920522\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920522","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Capacitor-coupled complementary emitter-follower for ultra-high-speed low-power bipolar logic circuits
A complementary emitter follower composed of a direct-coupled npn transistor and a capacitor-coupled pnp transistor is proposed. Low power dissipation and good noise removing capability can be obtained by this coupling scheme. An ECL gate with this complementary emitter follower is 63% faster and has 4 times better load driving capability than a conventional ECL gate.