Y. Takai, M. Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Y. Fukuzo, H. Watanabe
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引用次数: 35
摘要
3.3 V 512 k/spl倍/18/spl倍/2组同步DRAM采用新颖的3级流水线架构。通常采用模拟方式设计的地址访问路径经过数字化处理，通过列开关和数据输出缓冲器处的锁存电路将其分为三级。由于这种架构不需要额外的读/写总线和数据放大器，它最大限度地减少了芯片尺寸的增加。使用标准化的GTL接口，实现了250 Mbyte/s的同步DRAM，其芯片尺寸几乎与传统DRAM相同。
250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture
A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.
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