A 12 bit 600 kS/s digitally self-calibrated pipeline algorithmic ADC

Abstract

This paper describes an algorithmic A/D converter which employs digital error correction and self-calibration. In this paper, an approach is described that employs a nominal radix 2, 1.5 bit/stage conversion algorithm. The technique discussed in this paper can be applied to any cyclic or pipelined algorithmic converter, does not require extra clock cycles during the conversion, and no additional analog circuitry is needed. The analog circuit is extremely simple, using one operational amplifier and two latches per stage.