T. Yamagata, Hirotoshi Sato, K. Fujita, Y. Nishimura, K. Anami
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A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond
A Distributed Globally Replaceable Redundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.
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