2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第5页

Theory of Ising Machines and a Common Software Platform for Ising Machines 伊辛机理论与伊辛机通用软件平台

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045126

Shu Tanaka, Yoshiki Matsuda, N. Togawa

引用次数: 10

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture 面向区域高效的光神经网络:一种基于fft的结构

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045156

Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, D. Pan

引用次数: 43

An Adaptive Electromigration Assessment Algorithm for Full-chip Power/Ground Networks 全芯片电源/地网络的自适应电迁移评估算法

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045102

Shaobin Ma, Xiaoyi Wang, S. Tan, Liang Chen, Jian He

引用次数: 1

Security Threats and Countermeasures for Approximate Arithmetic Computing 近似算术计算的安全威胁与对策

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045385

Pruthvy Yellu, M. Monjur, Timothy Kammerer, Dongpeng Xu, Qiaoyan Yu

引用次数: 8

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques 使用分类器和CNN技术在平面图和布局中基于模板的PDN合成

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045303

Vidya A. Chhabria, A. Kahng, Minsoo Kim, U. Mallappa, S. Sapatnekar, Bangqi Xu

{"title":"Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques","authors":"Vidya A. Chhabria, A. Kahng, Minsoo Kim, U. Mallappa, S. Sapatnekar, Bangqi Xu","doi":"10.1109/ASP-DAC47756.2020.9045303","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045303","url":null,"abstract":"Designing an optimal power delivery network (PDN) is a time-intensive task that involves many iterations. This paper proposes a methodology that employs a library of predesigned, stitchable templates, and uses machine learning (ML) to rapidly build a PDN with region-wise uniform pitches based on these templates. Our methodology is applicable at both the floorplan and placement stages of physical implementation. (i) At the floorplan stage, we synthesize an optimized PDN based on early estimates of current and congestion, using a simple multilayer perceptron classifier. (ii) At the placement stage, we incrementally optimize an existing PDN based on more detailed congestion and current distributions, using a convolution neural network. At each stage, the neural network builds a safe-by-construction PDN that meets IR drop and electromigration (EM) specifications. On average, the optimization of the PDN brings an extra 3% of routing resources, which corresponds to a thousands of routing tracks in congestion-critical regions, when compared to a globally uniform PDN, while staying within the IR drop and EM limits.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132763881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Establishing Reachset Conformance for the Formal Analysis of Analog Circuits 模拟电路形式化分析的Reachset一致性建立

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045120

Niklas Kochdumper, Ahmad Tarraf, Malgorzata Rechmal, M. Olbrich, L. Hedrich, M. Althoff

引用次数: 9

Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits 模拟和SRAM电路良率优化的贝叶斯方法

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045614

Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng

{"title":"Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits","authors":"Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng","doi":"10.1109/ASP-DAC47756.2020.9045614","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045614","url":null,"abstract":"As the technology node shrinks to the nanometer scale, process variation become one of the most important issues in IC designs. The industry calls for designs with high yield under process variations. Yield optimization is computationally intensive because traditionally it relies on the Monte-Carlo yield estimation. In this paper, we will first review the Bayesian methods that reduce the computational cost of yield estimation and optimization. By applying Bayes’ theorem, maximizing the circuit yield is transformed to identify the design parameters with maximal probability density, conditioning on the event that the corresponding circuit is “pass”. It can thus avoid repetitive yield estimations during optimization. The computational cost can also be reduced by using the Bayesian optimization strategy. By using the Gaussian process surrogate model and adaptive yield estimation, Bayesian optimization can significantly reduce the number of simulations while achieving even comparable yields for analog and SRAM circuits. We further propose a Bayesian optimization approach for yield optimization via maxvalue entropy search in this paper. The proposed max-value entropy search can better explore the state space, and thus reduce the number of circuit simulations while achieving competitive results.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115618209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network Architectures 在迭代神经网络架构中解锁数据和价值重用

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045691

Maedeh Hemmat, Tejash Shah, Yuhua Chen, Joshua San Miguel

{"title":"CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network Architectures","authors":"Maedeh Hemmat, Tejash Shah, Yuhua Chen, Joshua San Miguel","doi":"10.1109/ASP-DAC47756.2020.9045691","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045691","url":null,"abstract":"A common inefficiency in traditional Convolutional Neural Network (CNN) architectures is that they do not adapt to variations in inputs. Not all inputs require the same amount of computation to be correctly classified, and not all of the weights in the network contribute equally to generate the output. Recent work introduces the concept of iterative inference, enabling per-input approximation. Such an iterative CNN architecture clusters weights based on their importance and saves significant power by incrementally fetching weights from off-chip memory until the classification result is accurate enough. Unfortunately, this comes at a cost of increased execution time since some inputs need to go through multiple rounds of inference, negating the savings in energy. We propose Cache Reuse Approximation for Neural Iterative Architectures (CRANIA) to overcome this inefficiency. We recognize that the re-execution and clustering built into these iterative CNN architectures unlock significant temporal data reuse and spatial value reuse, respectively. CRANIA introduces a lightweight cache+compression architecture customized to the iterative clustering algorithm, enabling up to 9 × energy savings and speeding up inference by 5.8 × with only 0.3% area overhead.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

WEID: Worst-case Error Improvement in Approximate Dividers WEID:近似除法的最坏情况误差改进

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045504

Hassaan Saadat, Haris Javaid, A. Ignjatović, S. Parameswaran

引用次数: 0

Scaled Population Arithmetic for Efficient Stochastic Computing 高效随机计算的比例总体算法

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045292

He Zhou, S. Khatri, Jiang Hu, Frank Liu

引用次数: 5