WEID: Worst-case Error Improvement in Approximate Dividers

Hassaan Saadat, Haris Javaid, A. Ignjatović, S. Parameswaran
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Abstract

Approximate integer dividers suffer from unreasonably high worst-case relative errors (such as 50% or 100%), which can adversely affect the application-level output. In this paper, we propose WEID, which is a novel lightweight method to improve the worst-case relative errors in approximate integer dividers. We first present an in-depth analysis to gain insights into the cause of the high worst-case relative error. Based on our insights, we propose a novel method to detect when an error occurs in an approximate divider, and modify the output to reduce the error. Further, we present the hardware realization of WEID method and demonstrate that it can be generically coupled with several state-of-the-art approximate dividers. Our results show that for 32-by-16 dividers, WEID reduces worst-case relative errors from 100% to $\sim 20$%, while still achieving $\sim 80$% and $\sim 70$% reduction in delay and energy compared to an accurate array divider.
WEID:近似除法的最坏情况误差改进
近似整数除法的最坏情况相对误差高得不合理(例如50%或100%),这可能对应用程序级输出产生不利影响。本文提出了一种新的轻量级方法WEID来改善近似整数除法的最坏情况相对误差。我们首先进行了深入的分析,以深入了解高最坏情况相对误差的原因。基于我们的见解,我们提出了一种新的方法来检测近似分频器中何时出现误差,并修改输出以减小误差。此外,我们提出了WEID方法的硬件实现,并证明它可以与几种最先进的近似分频器一般耦合。我们的研究结果表明,对于32 × 16分频器,WEID将最坏情况下的相对误差从100%降低到20%,同时与精确的阵列分频器相比,延迟和能量仍然降低了80%和70%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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