2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献

Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition 灭霸:基于交叉分解的高性能CPU-GPU均衡图分区

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045588

Dae-Hee Kim, R. Nagi, Deming Chen

引用次数: 1

A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System 三维堆叠系统中信号与电源互连的数量评估与重构机制

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045169

Ching-Hwa Cheng

{"title":"A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System","authors":"Ching-Hwa Cheng","doi":"10.1109/ASP-DAC47756.2020.9045169","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045169","url":null,"abstract":"Due to the high integration required for system application, the three-dimensional chip may resolve this requirement. The three-dimensional vertically stacking (3D-stacking) systems have been proposed to satisfy these requirements. However, the 3D-stacking system contains several design risks from its long layer interconnections. For a 3D-stacking system, it is difficult to identify where the numerous power and signal-interconnection are open-, shorted-fault, or resistive-short has accrued. Therefore, solving these interconnection problems is necessary. A feasible interconnection quality-evaluation, fault-diagnosis, and connection-reconfigurable mechanism are proposed. The proposed interconnection-measurement-recovery (IMR) mechanism will make it easy to find interconnection faults and make recovery in 3D-Stacking systems. The proposed IMR can detect interconnection open, short, bridge and resistive defects with the path-reroute mechanism. Future more, the signal transmission quality can be measured. This measurement provides to monitor signal propagation in pico-second accuracy. IMR has less extra area and power consumption overhead. The feasibilities of the proposed mechanism have been justified by 2D-chip and 3D-stacking MorPack both systems.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121234328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs 基于NoC的mpsoc性能增强的跟踪缓冲区重用

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045570

Sidhartha Sankar Rout, M. Badri, Sujay Deb

引用次数: 4

Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks Accelerator 为提高全量化神经网络加速器的精度设计高效快捷体系结构

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045739

Baoting Li, Longjun Liu, Yan-ming Jin, Peng Gao, Hongbin Sun, Nanning Zheng

引用次数: 0

Automated Trigger Activation by Repeated Maximal Clique Sampling 通过重复最大团抽样自动触发激活

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045449

Yangdi Lyu, P. Mishra

引用次数: 18

FTT-NAS: Discovering Fault-Tolerant Neural Architecture FTT-NAS:发现容错神经结构

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045324

Xuefei Ning, Guangjun Ge, Wenshuo Li, Zhenhua Zhu, Yin Zheng, Xiaoming Chen, Zhen Gao, Yu Wang, Huazhong Yang

{"title":"FTT-NAS: Discovering Fault-Tolerant Neural Architecture","authors":"Xuefei Ning, Guangjun Ge, Wenshuo Li, Zhenhua Zhu, Yin Zheng, Xiaoming Chen, Zhen Gao, Yu Wang, Huazhong Yang","doi":"10.1109/ASP-DAC47756.2020.9045324","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045324","url":null,"abstract":"With the fast evolvement of deep-learning specific embedded computing systems, applications powered by deep learning are moving from the cloud to the edge. When deploying NNs onto the edge devices under complex environments, there are various types of possible faults: soft errors caused by atmospheric neutrons and radioactive impurities, voltage instability, aging, temperature variations, and malicious attackers. Thus the safety risk of deploying neural networks at edge computing devices in safety-critic applications is now drawing much attention. In this paper, we implement the random bit-flip, Gaussian, and Salt-and-Pepper fault models and establish a multi-objective fault-tolerant neural architecture search framework. On top of the NAS framework, we propose Fault-Tolerant Neural Architecture Search (FT-NAS) to automatically discover convolutional neural network (CNN) architectures that are reliable to various faults in nowadays edge devices. Then we incorporate fault-tolerant training (FTT) in the search process to achieve better results, which we called FTT-NAS. Experiments show that the discovered architecture FT-NAS-Net and FTT-NAS-Net outperform other hand-designed baseline architectures (58.1%/86.6% VS. 10.0%/52.2%), with comparable FLOPs and less parameters. What is more, the architectures trained under a single fault model can also defend against other faults. By inspecting the discovered architecture, we find that there are redundant connections learned to protect the sensitive paths. This insight can guide future fault-tolerant neural architecture design, and we verify it by a modification on ResNet-20–ResNet-M.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations 通过RTL实现的定量评估来设计EM侧信道安全性

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045426

Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin

引用次数: 6

Improved DD-based Equivalence Checking of Quantum Circuits 改进的基于dd的量子电路等效性检验

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045153

Lukas Burgholzer, R. Wille

{"title":"Improved DD-based Equivalence Checking of Quantum Circuits","authors":"Lukas Burgholzer, R. Wille","doi":"10.1109/ASP-DAC47756.2020.9045153","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045153","url":null,"abstract":"Quantum computing is gaining considerable momentum through the recent progress in physical realizations of quantum computers. This led to rather sophisticated design flows in which the originally specified quantum functionality is compiled through different abstractions. This increasingly raises the question whether the respectively resulting quantum circuits indeed realize the originally intended function. Accordingly, efficient methods for equivalence checking are gaining importance. However, existing solutions still suffer from significant shortcomings such as their exponential worst case performance and an increased effort to obtain counterexamples in case of non-equivalence. In this work, we propose an improved DD-based equivalence checking approach which addresses these shortcomings. To this end, we utilize decision diagrams and exploit the fact that quantum operations are inherently reversible - allowing for dedicated strategies that keep the overhead moderate in many cases. Experimental results confirm that the proposed strategies lead to substantial speed-ups – allowing to perform equivalence checking of quantum circuits factors or even magnitudes faster than the state of the art.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114553339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Capacitance Extraction and Power Grid Analysis Using Statistical and AI Methods 利用统计和人工智能方法进行电容提取和电网分析

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045462

Wenjian Yu, Ming Yang, Yao Feng, Ganqu Cui, B. Gu

引用次数: 1

Soft Error and Its Countermeasures in Terrestrial Environment 陆地环境下的软误差及其对策

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045161

M. Hashimoto, Wang Liao

引用次数: 8