Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits

As the technology node shrinks to the nanometer scale, process variation become one of the most important issues in IC designs. The industry calls for designs with high yield under process variations. Yield optimization is computationally intensive because traditionally it relies on the Monte-Carlo yield estimation. In this paper, we will first review the Bayesian methods that reduce the computational cost of yield estimation and optimization. By applying Bayes’ theorem, maximizing the circuit yield is transformed to identify the design parameters with maximal probability density, conditioning on the event that the corresponding circuit is “pass”. It can thus avoid repetitive yield estimations during optimization. The computational cost can also be reduced by using the Bayesian optimization strategy. By using the Gaussian process surrogate model and adaptive yield estimation, Bayesian optimization can significantly reduce the number of simulations while achieving even comparable yields for analog and SRAM circuits. We further propose a Bayesian optimization approach for yield optimization via maxvalue entropy search in this paper. The proposed max-value entropy search can better explore the state space, and thus reduce the number of circuit simulations while achieving competitive results.