2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第6页

An Inductively Coupled Wireless Bus for Chiplet-Based Systems 基于芯片系统的感应耦合无线总线

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045184

J. Kadomoto, Satoshi Mitsuno, H. Irie, S. Sakai

引用次数: 2

Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing 并行计算中基于无线/有线混合NoC的高效屏障同步广播机制

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045503

H. Mondal, Navonil Chatterjee, R. Cataldo, J. Diguet

{"title":"Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing","authors":"H. Mondal, Navonil Chatterjee, R. Cataldo, J. Diguet","doi":"10.1109/ASP-DAC47756.2020.9045503","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045503","url":null,"abstract":"Parallel computing is essential to achieve the manycore architecture performance potential, since it utilizes the parallel nature provided by the hardware for its computing. These applications will inevitably have to synchronize its parallel execution: for instance, broadcast operations for barrier synchronization. Conventional network-on-chip architectures for broadcast operations limit the performance as the synchronization is affected significantly due to the critical path communications that increase the network latency and degrade the performance drastically. A Wireless network-on-chip offers a promising solution to reduce the critical path communication bottlenecks of such conventional architectures by providing hardware broadcast support. We propose efficient barrier synchronization support using hybrid wireless/wired NoC to reduce the cost of broadcast operations. The proposed architecture reduces the barrier synchronization cost up to 42.79% regarding network latency and saves up to 42.65% communication energy consumption for a subset of applications from the PARSEC benchmark.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122795993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA Biochips* 面向可靠性的IEEE Std. 1687 MEDA生物芯片的网络设计和块感知高级合成*

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045182

Zhanwei Zhong, Tung-Che Liang, K. Chakrabarty

引用次数: 5

JIT-Based Context-Sensitive Timing Simulation for Efficient Platform Exploration 基于jit的高效平台勘探上下文敏感时序仿真

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045255

Alessandro Cornaglia, Md. Shakib Hasan, A. Viehl, O. Bringmann, W. Rosenstiel

引用次数: 3

Software-Based Memory Analysis Environments for In-Memory Wear-Leveling 基于软件的内存损耗均衡分析环境

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045418

Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, G. V. D. Brüggen, S. Blömeke, Jian-Jia Chen

{"title":"Software-Based Memory Analysis Environments for In-Memory Wear-Leveling","authors":"Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, G. V. D. Brüggen, S. Blömeke, Jian-Jia Chen","doi":"10.1109/ASP-DAC47756.2020.9045418","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045418","url":null,"abstract":"Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear-leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"14 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114088217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Formal Semantics of Predictable Pipelines: a Comparative Study 可预测管道的形式语义:比较研究

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045351

M. Jan, Mihail Asavoae, Martin Schoeberl, Edward A. Lee

引用次数: 7

A Reconfigurable Approximate Multiplier for Quantized CNN Applications 用于量化CNN应用的可重构近似乘法器

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045176

Chuliang Guo, Li Zhang, Xian Zhou, Weikang Qian, Cheng Zhuo

{"title":"A Reconfigurable Approximate Multiplier for Quantized CNN Applications","authors":"Chuliang Guo, Li Zhang, Xian Zhou, Weikang Qian, Cheng Zhuo","doi":"10.1109/ASP-DAC47756.2020.9045176","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045176","url":null,"abstract":"Quantized CNNs, featured with different bit-widths at different layers, have been widely deployed in mobile and embedded applications. The implementation of a quantized CNN may have multiple multipliers at different precisions with limited resource reuse or one multiplier at higher precision than needed causing area overhead. It is then highly desired to design a multiplier by accounting for the characteristics of quantized CNNs to ensure both flexibility and energy efficiency. In this work, we present a reconfigurable approximate multiplier to support multiplications at various precisions, i.e., bit-widths. Moreover, unlike prior works assuming uniform distribution with bit-wise independence, a quantized CNN may have centralized weight distribution and hence follow a Gaussian-like distribution with correlated adjacent bits. Thus, a new block-based approximate adder is also proposed as part of the multiplier to ensure energy efficient operation with awareness of bit-wise correlation. Our experimental results show that the proposed adder significantly reduces the error rate by 76-98% over a state-of-the-art approximate adder for such scenarios. Moreover, with the deployment of the proposed multiplier, which is 17% faster and 22% more power saving than a Xilinx multiplier IP at the same precision, a quantized CNN implemented in FPGA achieves 17% latency reduction and 15% power saving compared with a full precision case.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128981520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem CMOS退火炉:组合优化问题的特定领域架构

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045326

C. Yoshimura, Masato Hayashi, Takashi Takemoto, M. Yamaoka

引用次数: 6

HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor HashHeat:基于O(C)复杂度哈希的动态视觉传感器滤波器

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045268

Shasha Guo, Ziyang Kang, Lei Wang, Shiming Li, Weixia Xu

引用次数: 8

Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and Augmentation 基于输入变形和增强的深度神经网络对抗性攻击

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045107

Pengfei Qiu, Qian Wang, Dongsheng Wang, Yongqiang Lyu, Zhaojun Lu, G. Qu

{"title":"Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and Augmentation","authors":"Pengfei Qiu, Qian Wang, Dongsheng Wang, Yongqiang Lyu, Zhaojun Lu, G. Qu","doi":"10.1109/ASP-DAC47756.2020.9045107","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045107","url":null,"abstract":"Typical Deep Neural Networks (DNN) are susceptible to adversarial attacks that add malicious perturbations to input to mislead the DNN model. Most of the state-of-theart countermeasures concentrate on the defensive distillation or parameter re-training, which require prior knowledge of the target DNN and/or the attacking methods and hence greatly limit their generality and usability. In this paper, we propose to defend against adversarial attacks by utilizing the input deformation and augmentation techniques that are currently widely utilized to enlarge the dataset during DNN’s training phase. This is based on the observation that certain input deformation and augmentation methods will have little or no impact on DNN model’s accuracy, but the adversarial attacks will fail when the maliciously induced perturbations are randomly deformed. We also use the ensemble of decisions to further improve DNN model’s accuracy and the effectiveness of defending various attacks. Our proposed mitigation method is model independent (i.e. it does not require additional training, parameter finetuning, or any structure modifications of the target DNN model) and attack independent (i.e., it does not require any knowledge of the adversarial attacks). So it has excellent generality and usability. We conduct experiments on standard CIFAR-10 dataset and three representative adversarial attacks: Fast Gradient Sign Method, Carlini and Wagner, and Jacobian-based Saliency Map Attack. Results show that the average success rate of the attacks can be reduced from 96.5% to 28.7% while the DNN model accuracy is improved by about 2%.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"672 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126722776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5