2021 22nd International Symposium on Quality Electronic Design (ISQED)最新文献

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Conditional Classification: A Solution for Computational Energy Reduction 条件分类:一种减少计算能量的方法
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424280
Ali Mirzaeian, Sai Manoj Pudukotai Dinakarrao, Ashka Vakil, H. Homayoun, Avesta Sasan
{"title":"Conditional Classification: A Solution for Computational Energy Reduction","authors":"Ali Mirzaeian, Sai Manoj Pudukotai Dinakarrao, Ashka Vakil, H. Homayoun, Avesta Sasan","doi":"10.1109/ISQED51717.2021.9424280","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424280","url":null,"abstract":"Deep convolutional neural networks have shown high efficiency in computer visions and other applications. However, with the increase in the depth of the networks, the computational complexity is growing exponentially. In this paper, we propose a novel solution to reduce the computational complexity of convolutional neural network models used for many class image classification. Our proposed technique breaks the classification task into two steps: 1) coarse-grain classification, in which the input samples are classified among a set of hyper-classes, 2) fine-grain classification, in which the final labels are predicted among those hyper-classes detected at the first step. We illustrate that our proposed classifier can reach the level of accuracy reported by the best in class classification models with less computational complexity (Flop Count) by only activating parts of the model that are needed for the image classification.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127632872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic Generation of Translators for Packet-Based and Emerging Protocols 基于分组和新兴协议的自动生成翻译器
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424338
Brian Crafton, A. Raychowdhury, S. Lim
{"title":"Automatic Generation of Translators for Packet-Based and Emerging Protocols","authors":"Brian Crafton, A. Raychowdhury, S. Lim","doi":"10.1109/ISQED51717.2021.9424338","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424338","url":null,"abstract":"A recent trend in open source hardware and chipletbased IP reuse faces a key obstacle: protocol standardization. Hardware interfaces lack flexibility and require designers to follow a strict behavior when implementing IP. The rigid nature of hardware interfaces prevents IP reuse, a critical challenge in integrating a plethora of emerging open source IP. To mitigate these challenges, we propose a tool to automatically synthesize translators between arbitrary IP blocks. Using a protocol description language (PDL), we model protocols such that they can be interpreted as finite state machines (FSM). Next, we design algorithms to map and schedule transactions between these protocols, generating a single integrated state machine which serves as a translator between the two protocols. Lastly, we convert our integrated state machine into readable RTL (Verilog) and perform functional verification. Our flow has been implemented, tested, and proven on 12 protocol pairs with unique behavior.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132684976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs 基于忆阻器的新型非易失D锁存器和触发器设计
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424269
Zhenxing Chang, Aijiao Cui, Ziming Wang, G. Qu
{"title":"Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs","authors":"Zhenxing Chang, Aijiao Cui, Ziming Wang, G. Qu","doi":"10.1109/ISQED51717.2021.9424269","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424269","url":null,"abstract":"Sequential devices are the fundamental building blocks for almost all digital electronic systems with memory. Due to the importance of instant data recovery after unexpected data loss such as unplanned power down, sequential devices need to have the nonvolatile property, which motivates the recent research and practice in integrating the nonvolatile memristor into CMOS devices. In this paper, we study how to apply this approach to improve the quality of nonvolatile D latch. Unlike the structure of conventional design, the proposed D latch consists of only one memristor, several transmission gates, and CMOS inverters. Our design overcomes the negative effect due to the threshold loss of the transistors. As simulation shows, compared with the current designs, our proposed memristor-based D latch can support the memristor to switch between different resistance states 2.3X-3.6X faster, and thus achieving a clock of higher frequency. In addition, our design allows the threshold value of the memristor to be selected from a much wider range. As an application, we use the proposed memristor-based D latch to implement a nonvolatile master-slave D flip-flop, which has smaller delay than all the state-of the-art designs and smaller area than all but one of them. Our designs improve the quality of memristor-based D latch and D flip-flop in terms of latency, area, and flexibility of threshold voltage selection, making them a promising option for data backup in real life systems.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132941094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference 基于贝叶斯推理的细胞感知顾客退货诊断
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424337
S. Mhamdi, P. Girard, A. Virazel, A. Bosio, A. Ladhar
{"title":"Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference","authors":"S. Mhamdi, P. Girard, A. Virazel, A. Bosio, A. Ladhar","doi":"10.1109/ISQED51717.2021.9424337","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424337","url":null,"abstract":"This paper presents a new cell-aware diagnosis flow that can be used to address a specific scenario (test protocol) one may encounter during diagnosis of customer returns. In this flow, we use a Bayesian classification method to precisely identify defect candidates. Experiments done on benchmark circuits as well as on a test chip from STMicroelectronics have proven the efficacy of our flow in terms of diagnosis accuracy and resolution.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"75 50","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection 利用偏置电压变化和阶数统计选择比较器的Flash ADC
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424288
T. Kitamura, Mahfuzul Islam, T. Hisakado, O. Wada
{"title":"Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection","authors":"T. Kitamura, Mahfuzul Islam, T. Hisakado, O. Wada","doi":"10.1109/ISQED51717.2021.9424288","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424288","url":null,"abstract":"High-speed flash ADCs are required for wireless communication systems. However, the trade-off between area, power, and linearity suffers severely by offset voltage variation in sub-micron process. This paper proposes a flash ADC architecture that utilizes the offset voltage variation to reduce area and power consumption by eliminating reference generation. The proposed architecture utilizes offset voltages as references by selecting the appropriate comparators after an on-chip calibration. The on-chip calibration is performed based on order statistics that allows evaluating offset voltages in the time-domain. We verify our proposed architecture by HSPICE simulation based on a commercial 65 nm process. Our proposed architecture realizes a 5-bit ADC with the power consumption of less than 1 mW at 2 GS/s of operation, excluding the encoder.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114584545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An End-to-end Multi-task Object Detection using Embedded GPU in Autonomous Driving 基于嵌入式GPU的自动驾驶端到端多任务目标检测
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424308
Shangli Zhou, Mimi Xie, Yufang Jin, Fei Miao, Caiwen Ding
{"title":"An End-to-end Multi-task Object Detection using Embedded GPU in Autonomous Driving","authors":"Shangli Zhou, Mimi Xie, Yufang Jin, Fei Miao, Caiwen Ding","doi":"10.1109/ISQED51717.2021.9424308","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424308","url":null,"abstract":"Autonomous driving has gained popularity due to its high reliability compared to human drivers. Autonomous vehicles combine variety of sensors to perceive their surroundings, and use deep learning (DL) to extract complicated information from the sensing data. However, there are several challenges: Many DL models have explosive model sizes, and therefore not only time consuming but also power consuming when implementing on embedded systems on vehicles, further degrading the battery life-cycle. The current on-board AI treats lane detection and car location separately. In this paper, we propose an end-to-end multi-task environment detection framework. We fuse the 3D point cloud object detection model and lane detection model, with model compression technique applied. As on-board sensors forward information to the multi-task network, it not only parallel two detection tasks to extract combination information, but also reduces entire running time of the DL model. Experiments show by adding the model compression technique, the running speed of multi-task model improves more than $2times$. Also, running time of lane detection model on Nvidia Jetson TX2 is almost $6times$ less comparing with running on CPU, which shows reasonableness of using embedded AI computing device on autonomous vehicle.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122997968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI 基于rram边缘人工智能的权值剪枝和差分横杆映射提高DNN容错性
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424332
Geng Yuan, Zhiheng Liao, Xiaolong Ma, Yuxuan Cai, Zhenglun Kong, Xuan Shen, Jingyan Fu, Zhengang Li, Chengming Zhang, Hongwu Peng, Ning Liu, Ao Ren, Jinhui Wang, Yanzhi Wang
{"title":"Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI","authors":"Geng Yuan, Zhiheng Liao, Xiaolong Ma, Yuxuan Cai, Zhenglun Kong, Xuan Shen, Jingyan Fu, Zhengang Li, Chengming Zhang, Hongwu Peng, Ning Liu, Ao Ren, Jinhui Wang, Yanzhi Wang","doi":"10.1109/ISQED51717.2021.9424332","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424332","url":null,"abstract":"Recent research demonstrated the promise of using resistive random access memory (ReRAM) as an emerging technology to perform inherently parallel analog domain in-situ matrix-vector multiplication—the intensive and key computation in deep neural networks (DNNs). However, hardware failure, such as stuck-at-fault defects, is one of the main concerns that impedes the ReRAM devices to be a feasible solution for real implementations. The existing solutions to address this issue usually require an optimization to be conducted for each individual device, which is impractical for mass-produced products (e.g., IoT devices). In this paper, we rethink the value of weight pruning in ReRAM-based DNN design from the perspective of model fault tolerance. And a differential mapping scheme is proposed to improve the fault tolerance under a high stuck-on fault rate. Our method can tolerate almost an order of magnitude higher failure rate than the traditional two-column method in representative DNN tasks. More importantly, our method does not require extra hardware cost compared to the traditional two-column mapping scheme. The improvement is universal and does not require the optimization process for each individual device.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123969120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
SolicitudeSavvy: An IoT-based Edge Intelligent Framework for Monitoring Anxiety in Real-time SolicitudeSavvy:一个基于物联网的边缘智能框架,用于实时监测焦虑
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424302
P. Sundaravadivel, Parker Wilmoth, Ashton Fitzgerald
{"title":"SolicitudeSavvy: An IoT-based Edge Intelligent Framework for Monitoring Anxiety in Real-time","authors":"P. Sundaravadivel, Parker Wilmoth, Ashton Fitzgerald","doi":"10.1109/ISQED51717.2021.9424302","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424302","url":null,"abstract":"Anxiety disorders affect more than 18 percent of the population and is the most common mental illnesses in the US. There is a great demand to address this emerging epidemic with tools to differentiate and diagnose such disorders, and to create awareness especially in places like NorthEast Texas which is home to 1.5 million people with 58 percent of them living in rural areas. The goal of the proposed device is to diagnose as many anxiety disorders as possible, in real-time using the diagnosing wearable framework, SolicitudeSavvy, which uses technology such as the Internet of Things (IoT), a network of interconnected devices, to accomplish such a task. The proposed IoT-based device has two components: a custom-built wearable necklace that contains sensors to collect data about the user as they go about their day and a low-cost portable system that monitors Electrooculography (EoG) signal using a camera. The partial necklace attaches to the shirt and opens halfway around the wearer's neck and the EoG can be attached to any eyewear. The device monitors the user throughout the day, and even as they go to bed at night. This information is accumulated in the IoT cloud and analyzed to see exactly what type of disorder(s) the patient may suffer from. The authorized personnel i.e. doctor or therapist, can use this pattern to find a treatment that best suits them and is most likely to resolve their affliction.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128285007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion SeNonDiv:使用混合存储器和关键数据转移保护非易失性存储器
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424292
Arijit Nath, Manik B. Bhosle, H. Kapoor
{"title":"SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion","authors":"Arijit Nath, Manik B. Bhosle, H. Kapoor","doi":"10.1109/ISQED51717.2021.9424292","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424292","url":null,"abstract":"The emerging Non-volatile memories are projected as alternatives of traditional DRAM-based main memories. However, their non-volatility feature leads to serious security vulnerabilities. The sensitive data stored in these memories can be easily taken away due to prolonged data retention. A wide variety of encryption-based techniques protect these data at the cost of harmful side effects of encryption algorithms like high encryption/decryption latency and increased encryption induced write activities. It launches a tug-of-war between security provisioning and system performance degradation as well as shortened lifetime of NVMs. In this paper, we propose a data-diversion based technique that protects the security-sensitive data of the applications by allocating the security critical pages in the volatile DRAM part of a DRAM-PCM hybrid main memory system on page faults. Experimental evaluation shows significant improvements in performance and lifetime compared to a partial encryption and a full encryption based technique.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121863937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Space Extrapolation for Power Delivery Networks using a Transposed Convolutional Net 基于转置卷积网络的输电网络空间外推设计
2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424309
O. W. Bhatti, M. Swaminathan
{"title":"Design Space Extrapolation for Power Delivery Networks using a Transposed Convolutional Net","authors":"O. W. Bhatti, M. Swaminathan","doi":"10.1109/ISQED51717.2021.9424309","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424309","url":null,"abstract":"The geometrical and material properties of distributed electromagnetic structures comprise the design space. This space characterizes the structure’s frequency response in complex domain. In this paper, we propose a machine learning framework for predicting frequency response of a power delivery network as a function of its extrapolated multidimensional geometrical and material parameters. The proposed approach comprises of an ensemble of architectures: (1) Fully Connected Upsampler for latent code generation (2) Convolutional Decoder to learn the frequency response from the latent code. The 14D design space is converted to a Lth dimensional code which entails the frequency response information. With the proposed architecture, a root mean squared error of 0.004 ohms is achieved when compared to the true value. We focus on extrapolation of design space parameters while training on in-band values. We also illustrate how frequency poles move with varying design space exploiting parameter sensitivity in different frequency bands.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130729769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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