2021 22nd International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

Runtime Long-Term Reliability Management Using Stochastic Computing in Deep Neural Networks 基于随机计算的深度神经网络运行时长期可靠性管理

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424285

Yibo Liu, Shuyuan Yu, Shaoyi Peng, S. Tan

{"title":"Runtime Long-Term Reliability Management Using Stochastic Computing in Deep Neural Networks","authors":"Yibo Liu, Shuyuan Yu, Shaoyi Peng, S. Tan","doi":"10.1109/ISQED51717.2021.9424285","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424285","url":null,"abstract":"In this paper, we propose a new dynamic reliability technique using an accuracy-reconfigurable stochastic computing (ARSC) framework for deep learning computing. Unlike the conventional stochastic computing that conducts design time accuracy power/energy trade-off, the new ARSC design can adjust the bit-width of the data in run time. Hence, the ARSC can mitigate the long-term aging effects by slowing the system clock frequency, while maintaining the inference throughput by reducing the data bit-width at a small cost of accuracy. We show how to implement the recently proposed counter-based SC multiplication and bit-width reduction on a layer-wise quantization scheme for CNN networks with dynamic fixed-point data. We validate an ARSC-based five-layer convolutional neural network design for the MNIST dataset based on Vivado HLS with constraints from Xilinx Zynq-7000 family xc7z045 platform. Experimental results show that new ARSC DNN can sufficiently compensate the NBTI induced aging effects in 10 years with marginal classification accuracy loss while maintaining or even exceeding the pre-aging computing throughput. At the same time, the proposed ARSC computing framework also reduces the active power consumption due to the frequency scaling, which can further improve system reliability due to the reduced temperature.Experimental results show that new ARSC DNN can sufficiently compensate the NBTI induced aging effects in 10 years with marginal classification accuracy loss while maintaining or even exceeding the preaging computing throughput. At the same time, the proposed ARSC computing framework also reduces the active power consumption due to large frequency scaling, which can further improve system reliability due to the reduced temperature.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132557055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Towards Row Sensitive DRAM Refresh through Retention Awareness 通过保留感知实现行敏感DRAM刷新

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424339

Tanmay Goel, Divyansh S. Maura, Kaustav Goswami, Shirshendu Das, D. Banerjee

{"title":"Towards Row Sensitive DRAM Refresh through Retention Awareness","authors":"Tanmay Goel, Divyansh S. Maura, Kaustav Goswami, Shirshendu Das, D. Banerjee","doi":"10.1109/ISQED51717.2021.9424339","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424339","url":null,"abstract":"Dynamic Random Access Memory (DRAM) is the de-facto choice for main memories in modern day computing systems. It is based on capacitor technology, which is volatile in nature. Hence, these memories require periodic refreshing, usually at 64 ms, in order to ensure data persistence. Refreshing results in blocking of the memory device for performing normal read or write operations. However, it has been found that not all cells of the device requires uniform refreshing at 64 ms. Due to shrinking of technologies, deviations are observed in nominal parameters which causes variations in retention and restoration time. In this paper, we propose a retention aware DRAM refreshing model, which is operated in auto-refresh (AR) mode of a DRAM device. We call the proposed model Lightweight Retention Time Aware Refreshing, or simply LRAR, which can be operated either in a deterministic or an approximate mode while consuming a constant amount of hardware space. The former ensures consumption of least possible area in comparison to previously proposed works. While the latter is aimed to incorporate periodic refreshing for a newly emerged DRAM phenomenon called Variable Retention Time, or, VRT, which uses the basics of approximation. After extensive evaluation, we find that our proposed model reduces execution time of programs up to 11% (9.4% on average). The memory system's energy consumption is also reduced by an average of 11.5%, and refresh energy by an average of 73.6%. We achieve the aforementioned gains at a modest area overhead of 7$,240 mu mathrm{m}^{2},(0.0018$% of a 400mm$^{2,}$die) and storage overhead.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130689352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches 基于多保留STT-RAM的最后一级缓存中基于写频率的动态分配

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424250

Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, H. Kapoor

{"title":"DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches","authors":"Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, H. Kapoor","doi":"10.1109/ISQED51717.2021.9424250","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424250","url":null,"abstract":"Spin-Transfer Torque RAM (STT-RAM) exhibits advantages like high density, non-volatility, and low leakage power consumption, making them a plausible successor to SRAM in caches. However, STT-RAM’s large write energy and latency constrain its potential for commercial usage in caches. Relaxing STTRAM’s retention time is one of the emerging and viable solutions to alleviate this roadblock, as this reduces the write time and energy. Reduction of retention time, however, leads to premature expiry of blocks requiring frequent refreshes or writebacks. These approaches cause unnecessary stalls and increase miss-rate.This paper proposes using a cache with partitions of different retention times. It further puts forth a block placement and reallocation policy to use these different partitions effectively. A block is said to be placed in an optimal partition if the block is either accessed or evicted before it expires. In particular, infrequently written blocks are allocated to higher retention time partitions, guaranteeing a reduction in block expiry/writebacks. During the execution, at regular intervals, blocks are migrated to appropriate retention time partitions depending on the application characteristics. Experimental evaluation shows significant improvement in performance and miss-rate compared to baseline allocation policies.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing 边缘计算中最小能量点跟踪与软实时调度的集成

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424343

Takumi Komori, Yutaka Masuda, Jun Shiomi, T. Ishihara

{"title":"Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing","authors":"Takumi Komori, Yutaka Masuda, Jun Shiomi, T. Ishihara","doi":"10.1109/ISQED51717.2021.9424343","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424343","url":null,"abstract":"In the upcoming Internet of Things era, reducing energy consumption of embedded processors is highly desired. Minimum Energy Point Tracking (MEPT) is one of the most efficient methods to reduce both dynamic and static energy consumption of a processor. Previous works proposed a variety of MEPT methods over the past years. However, none of them incorporate their algorithms with practical real-time operating systems, although edge computing applications often require low energy task execution with guaranteeing real-time properties. The difficulty comes from the time complexity for identifying MEP and changing voltages, which often prevents real-time task scheduling. This paper proposes an approximated MEPT algorithm, which reduces the complexity of identifying MEP down to that of Dynamic Voltage and Frequency Scaling (DVFS). We also propose a task scheduling algorithm, which adjusts processor performance to the workload, and provides a soft real-time capability to the system. With these two methods, MEPT became a general task, and the operating system stochastically adjusts the average response time of a processor to be equal to a specified deadline. The experiments using a fabricated test chip show that the energy loss induced by the proposed algorithm is only 0.5% at most, and the algorithm does not sacrifice the fundamental real-time properties.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124166932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Interactive IoT-based framework for Resource Management in Assisted living during pandemic 大流行期间辅助生活资源管理的交互式物联网框架

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424323

Parker Wilmoth, P. Sundaravadivel

{"title":"An Interactive IoT-based framework for Resource Management in Assisted living during pandemic","authors":"Parker Wilmoth, P. Sundaravadivel","doi":"10.1109/ISQED51717.2021.9424323","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424323","url":null,"abstract":"With a steady rise in the aging population, researchers predict that one out of every six people will be over the age of 65 by 2020. Seniors need to monitor their health consistently as chronic diseases such as diabetes, arthritis, dementia, are highly prevalent among them. This has lead to an increase in the use of devices such as sensors, cameras, and robots, with technologies such as artificial intelligence and the internet of medical things. These can help in designing innovative solutions for improving the daily life of seniors and helping them to be more independent. Though the recent advancements in technology can help in developing a better assisted living, the key challenge is to make a reliable framework that can help the consumer in using those product at ease. In challenging times, such as the current pandemic, the need for a framework that can help in reducing social interaction is particularly significant. In this paper, we discuss an interactive framework with the help of a smart camera and smart speakers that can help seniors to manage their essential resources at ease. This Internet of Things based framework can help seniors in having an organized inventory without ever needing to leave their home.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128260183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Defending Against Misspeculation-based Cache Probe Attacks Using Variable Record Table 基于可变记录表的缓存探测错误防范

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424259

Love Kumar Sah, S. A. Islam, S. Katkoori

引用次数: 0

Real-Time CNN Based ST Depression Episode Detection Using Single-Lead ECG 基于CNN的实时ST段抑郁发作单导联检测

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424275

E. Tiryaki, Akshay Sonawane, L. Tamil

引用次数: 3

Low-power Analog and Mixed-signal IC Design of Multiplexing Neural Encoder in Neuromorphic Computing 神经形态计算中复用神经编码器的低功耗模拟和混合信号集成电路设计

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424267

Honghao Zheng, Nima Mohammadi, Kangjun Bai, Y. Yi

{"title":"Low-power Analog and Mixed-signal IC Design of Multiplexing Neural Encoder in Neuromorphic Computing","authors":"Honghao Zheng, Nima Mohammadi, Kangjun Bai, Y. Yi","doi":"10.1109/ISQED51717.2021.9424267","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424267","url":null,"abstract":"The research on computing clusters comprising neuromorphic systems has drawn the interest of many researchers in the field. Neural encoding is a crucial component that determines how the information is conveyed through a train of spikes, greatly impacting the mode of operations’ and systems’ performance to a large extent. Numerous encoding schemes have been proposed in the literature, including latency encoding, ISI encoding, and phase encoding. Each of these schemes has its own benefits and shortcomings which brings up the idea to see if they can complement each other. Multiplexing encoding combines two different schemes with the aim of enhancing the performance via conveying more information, making the encoded spikes more robust against noise. In this paper, we introduce a mixed-signal IC design of multiplexing latency-phase encoder. A key principle of the multiplexing encoding, the gamma alignment, is employed to achieve enhanced functionality of spiking neurons supported by biological research. In the proposed encoding scheme, a set of predetermined spiking neurons, which can be perceived as dimensionality reduction over the grouped higher-dimensional stimuli, maps the input currents to latency spike trains. Consequently, these spike trains are aligned and then superimposed on each other to form the resulting spike train. The simulation result is carefully inspected for verification of the encoder. The introduced power-efficient circuit is designed with 180nm CMOS technology and, to the best of our knowledge, is the first IC design of the multiplexing latency-phase that is built upon two different encoding schemes. The power consumption of the encoder is generally proportional to the number of neurons, and for a 4-neuron structure, the layout-level simulation result shows the circuit consumes 10mW of power.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132468477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits 有限域算术电路的字级多固定可整流性

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424286

V. Rao, Irina Ilioaea, Haden Ondricek, P. Kalla, Florian Enescu

引用次数: 2

A Three-dimensional (3D) Memristive Spiking Neural Network (M-SNN) System 三维记忆脉冲神经网络(M-SNN)系统

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424303

Hongyu An, M. Al-Mamun, M. Orlowski, Yang Yi

{"title":"A Three-dimensional (3D) Memristive Spiking Neural Network (M-SNN) System","authors":"Hongyu An, M. Al-Mamun, M. Orlowski, Yang Yi","doi":"10.1109/ISQED51717.2021.9424303","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424303","url":null,"abstract":"The information communicating among neurons in Spiking Neural Networks (SNNs) is represented as spiking signals. The outstanding energy efficiency of SNNs stems from the minimal computational cost on the nonlinear calculations of the neurons and the communicating power between them. In this paper, we present a three-dimensional (3D) Memristive Spiking Neural Network (M-SNN) system which employs memristors not only as of the electronic synapse but also as the threshold function of SNNs. The simulation results demonstrate our fabricated two-layer memristors outperform the one-layer configuration on design area, power consumption, and latency with the factors of 2, 1.48, and 2.58. To alleviate the switching variation, the heat dissipation layers are added to our memristor resulting in a $sim$30% reduction in cycle-to-cycle variation. The performance of the 3DM-SNN system is evaluated through the benchmark dataset (CIFAR-10). Our memristive threshold function improves the power consumption by 36%, compared with other state-of-the-art memristor-based threshold functions. The low variation memristor-based synapse shows significant improvement (10% to 66%) on design area, power consumption, and latency, compared with the SRAM and other state-of-the-art memristive synapses.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125173470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0