2021 22nd International Symposium on Quality Electronic Design (ISQED)最新文献

{"title":"Fast and Accurate Library Generation Leveraging Deep Learning for OCV Modelling","authors":"Eunice Naswali, Namhoon Kim, Pravin Chandran","doi":"10.1109/ISQED51717.2021.9424316","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424316","url":null,"abstract":"Statistical timing characterization for modeling On-Chip Variation (OCV) is critical in current technology nodes to avoid over-design and to improve design convergence and predictability. OCV characterization, however, is resource intensive as it involves running millions of Monte-Carlo spice simulations to cover different timing arcs for multiple cells in standard-cell library. We have developed a neural network model that fully comprehends multiple cell types to model cell propagation delays as well as OCV sigma at target process-voltage-temperature (PVT) corners with a significantly reduced number of simulations. The proposed method generates Liberty Variation Format (LVF) models which are the latest and most accurate representation of OCV margin in the industry’s standard tools and flows.On extensive testing with 7 million OCV delay values in 10nm node, we attained 60% reduction in runtime while maintaining prediction-error less than 5% for 99.98% arcs which can be used for early timing integration.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators","authors":"Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, S. Natarajan, K. Basu","doi":"10.1109/ISQED51717.2021.9424301","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424301","url":null,"abstract":"The ever-increasing computing requirements of Deep Neural Networks (DNNs) have accentuated the deployment of such networks on hardware accelerators. Inference execution of large DNNs often manifests as an energy bottleneck in such accelerators, especially when used in resource-constrained Internet-of-Things (IoT) edge devices. This can be primarily attributed to the massive energy incurred in accessing millions of trained parameters stored in the on-chip memory, as demonstrated in existing research. To address this challenge, we propose HardCompress, which, to the best of our knowledge, is the first compression solution pertaining to commercial DNN accelerators. The three-step approach involves hardware-based post-quantization trimming of weights, followed by dictionary-based compression of the weights and subsequent decompression by a low-power hardware engine during inference in the accelerator. The efficiency of our proposed approach is evaluated on both lightweight networks trained on MNIST dataset and large DNNs trained on ImageNet dataset. Our results demonstrate that HardCompress, without any loss in accuracy on large DNNs, furnishes a maximum compression of 99.27%, equivalent to 137$times$ reduction in memory footprint in the systolic array-based DNN accelerator.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfiguring the Mux-Based Arbiter PUF using FeFETs","authors":"Srinivasa Ramanujam, W. Burleson","doi":"10.1109/ISQED51717.2021.9424328","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424328","url":null,"abstract":"Physical Unclonable Functions (PUFs) are lightweight security primitives that exploit complex manufacturing variations in integrated circuits to extract secret keys. It is well-established that the unique keys generated by the mux-based arbiter PUF can be predicted accurately using logistic regression (LR), provided a set of challenge-response pairs (CRPs) are known. The integration of 28nm HKMG FeFET with CMOS technology has been shown to neither alter the switching behavior of the FeFET, nor affect the baseline CMOS. In this work, we present simulation results that discuss the possibility of using the FeFET to design “stronger” arbiter PUFs that can be reconfigured at least 6n times, where n represents the number of stages. Results from LR based attacks suggest that the training dataset may need to be updated after every reconfiguration cycle, preventing the adversary from collecting enough training data for each configuration within a reasonable amount of time for a security breach.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115191342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Thermal Goodness Evaluation of a 3D-IC Floorplan","authors":"S. K. Vendra, M. Chrzanowska-Jeske","doi":"10.1109/ISQED51717.2021.9424278","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424278","url":null,"abstract":"High and unevenly spread 3D chip temperatures can be reduced when appropriate thermal-aware design is incorporated in early floorplanning. We developed a fast approach to evaluate thermal goodness of 3D floorplans. The proposed algorithm uses a power-based measure calculated using the impact of the heat from adjacent intra- and inter-layer modules. This approach significantly reduces runtime compared to temperature distribution simulation when thermal optimization is included in non-deterministic 3D-floorplanners. Usually, the goal is to minimize peak temperature and generate thermally-optimized 3D floorplans. Our results show that thermal quality factors generated by our model closely agree with factors generated by more accurate simulation-based thermal models, like HotSpot [1]. We achieve a correlation coefficient of 0.96 with HotSpot results and an average speed up of 29X on evaluation grid size of 64x64x4 for GSRC benchmarks. The sensitivity of the proposed algorithm to temperature difference between the 3D floorplans being compared and the success rate is also analyzed.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122601080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detection Limit for Intermediate Faults in Memristor Circuits","authors":"Rasika Joshi, J. Acken","doi":"10.1109/ISQED51717.2021.9424281","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424281","url":null,"abstract":"Memristor crossbar structures are widely used in logic, memory, security, and neuromorphic applications. It becomes necessary to test these devices for faults since they are prone to high defect densities. In this paper, we introduce a new terminology “intermediate faults” in memristor circuits. Intermediate faults are faults whose memristor resistance values lie between low resistance state (LRS) and High resistance state (HRS) values. This paper extends the fault detection method for HRS/LRS stuck-at faults to detecting intermediate faults using sneak paths in memristor circuits. We describe the importance of setting the detection limit for testing intermediate faults. Our simulation results present the detection limit value for intermediate resistances using five long and three long sneak paths in a 3x3 crossbar array. Our fault detection scheme can be used for detecting intermediate faults along with stuck-at low resistance and stuck-at high resistance faults.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121881884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology","authors":"Sachin Bhat, S. Ghosh, S. Kulkarni, Mingyu Li, C. A. Moritz","doi":"10.1109/ISQED51717.2021.9424282","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424282","url":null,"abstract":"Three-dimensional integrated circuits (3D-ICs) provide a feasible path for scaling CMOS technology in the foreseeable future. IMEC and IRDS roadmaps project that 3D integration is a key avenue for the IC industry beyond 2024. They project that some form of 3D-IC technology based on nanosheets/nanowires is likely to become mainstream soon. SkyBridge-3D-CMOS (S3DC) is one among the first vertical nanowire-based fine-grained 3D-IC directions which offers paradigm shift in technology scaling as well as design. Rather than die-die and layer-layer stacking, S3DC’s core aspects, from device to circuit style to interconnect, are co-architected in a 3D fabric-centered manner building on a uniform 3D nanowire template. Nanowire-based 3D-IC technologies such as S3DC solve most of the traditional scaling issues of 2D-CMOS but present new manufacturing challenges because of their complex 3D geometry. Therefore, for these directions to become mainstream, a robust wafer-scale manufacturing pathway that addresses these challenges is vital. In this paper, we propose a wafer-scale manufacturing pathway aimed at developing and optimizing the manufacturing process flows of S3DC. Using physics-driven virtual process integration functionalized with design and process parameters, we obtained realistic 3D structures for all the underlying IC elements and finally combined them to build 3D standard cells in S3DC. Electrical characterization of resultant structures using process and device simulations were performed while considering the material properties and nanoscale physics effects. Circuit-level simulations accounting for device behavior using SPICE-compatible compact model and circuit interconnect parasitics were carried out to study the impact of variations in process steps such as patterning, lithography, etch, deposition on device and interconnect performance. Our bottom-up simulation results indicate that the proposed pathway is robust enough to be adopted for large-scale production thus paving the way for wide-spread adoption of vertical fine-grained 3D-IC technologies.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129638010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Three-dimensional Memristive Deep Neural Network with Programmable Attention Mechanism","authors":"Hongyu An, Kangjun Bai, Yang Yi","doi":"10.1109/ISQED51717.2021.9424331","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424331","url":null,"abstract":"Attention Mechanism is a critical function of a neural network-based visual system that enables the human brain can devote computing effort to process desired information, concurrently ignoring undesired background noise intentionally. Through this signal processing methodology, the brain system achieves a remarkable energy efficiency. The significance of investigating the attention mechanism is to not only potentially reveal how the human brain comprehends visual signals but also to construct an attention-oriented power-efficient neuromorphic system. This paper proposes a hypothesis for the visual attention mechanism, derives a neural network model with mathematical equations, and realizes the circuit implementation with memristor and three-dimensional (3D) monolithic integration technology.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129887561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Trusted Electronic Systems with Untrusted COTS","authors":"Shuo Yang, Prabuddha Chakraborty, Patanjali Slpsk, S. Bhunia","doi":"10.1109/ISQED51717.2021.9424257","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424257","url":null,"abstract":"The challenges of custom integrated circuits (IC) design have made it prevalent to integrate commercial-off-the-shelf (COTS) components (micro-controllers, FPGAs, etc.) in today’s designs. While this approach eases the design challenges and improves productivity, it also gives rise to diverse security concerns. One such concern is the possibility of malicious hardware modifications, also called hardware Trojan attacks, by untrusted parties involved in the manufacturing or distribution of COTS devices. While Hardware Trojan detection is an active research topic in the field of microelectronics security, most methods assume the availability of a golden design/chip, which is impractical in the case of a COTS device. In this paper, we discuss challenges with detecting Trojan in COTS components, and introduce a Trojan detection method that applies unsupervised learning. We utilize side-channel power signatures to cluster and isolate chips with Trojans. The proposed method is suitable for trust verification of COTS components by an original equipment manufacturer (OEM) before system integration. In our method, the design house creates a set of security validation test vectors available to the tester (e.g., OEM). The OEM can also generate the test vectors using the block-level diagrams provided by the design house. Power signatures are generated for all the chips under test using these test vectors. We use the generated power signatures to apply feature extraction followed by clustering to group the chips into bins. Through this process, we divide the chips into distinct bins and distinguish the Trojan-inserted chips from the Trojan-free ones. The bin with golden chips can be identified by extensive testing and reverse engineering of one chip sampled from each bin. We utilize two clustering techniques K-Means, and Expectation-Maximization (EM) to perform a comparative analysis. Additionally, we perform extensive experiments to assert our method’s effectiveness and obtain over 98% accuracy on the clustering of FPGA chips with both combinational and sequential Trojans.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129910341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of Machine Learning in Hardware Trojan Detection","authors":"Shamik Kundu, Xingyu Meng, K. Basu","doi":"10.1109/ISQED51717.2021.9424362","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424362","url":null,"abstract":"Hardware Trojans (HTs), maliciously inserted in an integrated circuit during untrusted design or fabrication process pose critical threat to the system security. With the ever increasing capabilities of an adversary to subvert the system during run-time, it is imperative to detect the manifested Trojans in order to reinforce the trust in hardware. In this regard, Machine Learning (ML) algorithms, with their intrinsic capability to execute feature engineering at high learning rates, are emerging as promising candidates to be utilized by system defenders. In this paper, we explore Trojan detection mechanisms that are based on ML, and thereby investigate the prowess of the ML algorithms in bolstering system security. Furthermore, we analyze the efficiency of each proposed Trojan detection strategy based on the underlying ML algorithm. Finally, we underline some problems with existing Trojan detection approaches and discuss future research in the interest of improved performance of the employed ML algorithms, thus aiding in enhancing the intended hardware security.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123204036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SAC: A Novel Multi-hop Routing Policy in Hybrid Distributed IoT System based on Multi-agent Reinforcement Learning","authors":"Wen Zhang, Tao Liu, Mimi Xie, Jun Zhang, Chen Pan","doi":"10.1109/ISQED51717.2021.9424255","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424255","url":null,"abstract":"Energy harvesting (EH) IoT devices have attracted vast attention in both academia and industry as they can work sustainably by harvesting energy from the ambient environment. However, due to the weak and transient nature of harvesting power, EH technology is unable to support power-intensive IoT devices such as IoT edge servers. Therefore, the hybrid IoT system where the EH IoT devices and non-EH IoT devices co-exist is forthcoming. This paper explored the routing problem in such a hybrid distributed IoT system. We first proposed a comprehensive multi-hop routing mechanism of this hybrid system. After that, we proposed a distributed multi-agent deep reinforcement learning algorithm, known as spatial asynchronous advantage actor-critic (SAC), to optimize the system routing policy and energy allocation while maximizing the total amount of transmitted data and the overall data delivery to the sink node. The experiments indicate that SAC can averagely complete at least $sim 1.5 times$ transmission rate and $sim 12.9times$ Sink packet delivery rate compared with the baselines.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115900561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}