Fast Thermal Goodness Evaluation of a 3D-IC Floorplan

High and unevenly spread 3D chip temperatures can be reduced when appropriate thermal-aware design is incorporated in early floorplanning. We developed a fast approach to evaluate thermal goodness of 3D floorplans. The proposed algorithm uses a power-based measure calculated using the impact of the heat from adjacent intra- and inter-layer modules. This approach significantly reduces runtime compared to temperature distribution simulation when thermal optimization is included in non-deterministic 3D-floorplanners. Usually, the goal is to minimize peak temperature and generate thermally-optimized 3D floorplans. Our results show that thermal quality factors generated by our model closely agree with factors generated by more accurate simulation-based thermal models, like HotSpot [1]. We achieve a correlation coefficient of 0.96 with HotSpot results and an average speed up of 29X on evaluation grid size of 64x64x4 for GSRC benchmarks. The sensitivity of the proposed algorithm to temperature difference between the 3D floorplans being compared and the success rate is also analyzed.